diff --git a/formal_cover.gtkw b/formal_cover.gtkw deleted file mode 100644 index 4f0c807..0000000 --- a/formal_cover.gtkw +++ /dev/null @@ -1,141 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Thu Apr 6 11:31:18 2023 -[*] -[dumpfile] "/home/angelo/Videos/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd" -[dumpfile_mtime] "Thu Apr 6 11:30:02 2023" -[dumpfile_size] 69448 -[savefile] "/home/angelo/Videos/DDR3_Controller/formal_cover.gtkw" -[timestart] 0 -[size] 1848 1126 -[pos] -51 -51 -*-5.094873 174 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[sst_width] 43 -[signals_width] 468 -[sst_expanded] 0 -[sst_vpaned_height] 743 -@28 -ddr3_controller.i_clk -ddr3_controller.i_rst_n -ddr3_controller.i_wb_cyc -ddr3_controller.o_wb_stall -ddr3_controller.i_wb_stb -ddr3_controller.i_wb_we -@c00022 -ddr3_controller.f_index[4:0] -@28 -(0)ddr3_controller.f_index[4:0] -(1)ddr3_controller.f_index[4:0] -(2)ddr3_controller.f_index[4:0] -(3)ddr3_controller.f_index[4:0] -(4)ddr3_controller.f_index[4:0] -@1401200 --group_end -@200 -- -@22 -ddr3_controller.i_wb_addr[23:0] -ddr3_controller.i_wb_data[511:0] -ddr3_controller.i_wb_sel[63:0] -@28 -ddr3_controller.o_wb_ack -@200 -- -@28 -ddr3_controller.bank_status_q[7:0] -@22 -ddr3_controller.bank_active_row_q<0>[13:0] -ddr3_controller.bank_active_row_q<1>[13:0] -@24 -ddr3_controller.bank_active_row_q<2>[13:0] -@22 -ddr3_controller.bank_active_row_q<3>[13:0] -ddr3_controller.bank_active_row_q<4>[13:0] -ddr3_controller.bank_active_row_q<5>[13:0] -ddr3_controller.bank_active_row_q<6>[13:0] -ddr3_controller.bank_active_row_q<7>[13:0] -@200 -- --[0] = WR , [1] = ACT, [2] = RD, [3] = PRE -@22 -ddr3_controller.cmd_q<0>[20:0] -ddr3_controller.cmd_q<1>[20:0] -ddr3_controller.cmd_q<2>[20:0] -ddr3_controller.cmd_q<3>[20:0] -@200 -- -@28 -ddr3_controller.stage1_pending -ddr3_controller.stage1_bank[2:0] -@22 -ddr3_controller.stage1_row[13:0] -ddr3_controller.stage1_col[9:0] -@28 -ddr3_controller.stage1_next_bank[2:0] -@22 -ddr3_controller.stage1_next_row[13:0] -@28 -ddr3_controller.stage1_we -@200 -- -@28 -ddr3_controller.stage2_pending -ddr3_controller.stage2_bank[2:0] -@22 -ddr3_controller.stage2_row[13:0] -ddr3_controller.stage2_col[9:0] -@28 -ddr3_controller.stage2_we -@200 -- -@28 -ddr3_controller.reset_done -@200 -- --DELAYS -@22 -ddr3_controller.delay_before_precharge_counter_q<0>[3:0] -ddr3_controller.delay_before_precharge_counter_q<1>[3:0] -ddr3_controller.delay_before_precharge_counter_q<2>[3:0] -ddr3_controller.delay_before_precharge_counter_q<3>[3:0] -ddr3_controller.delay_before_precharge_counter_q<4>[3:0] -ddr3_controller.delay_before_precharge_counter_q<5>[3:0] -ddr3_controller.delay_before_precharge_counter_q<6>[3:0] -ddr3_controller.delay_before_precharge_counter_q<7>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_activate_counter_q<0>[3:0] -ddr3_controller.delay_before_activate_counter_q<1>[3:0] -ddr3_controller.delay_before_activate_counter_q<2>[3:0] -ddr3_controller.delay_before_activate_counter_q<3>[3:0] -ddr3_controller.delay_before_activate_counter_q<4>[3:0] -ddr3_controller.delay_before_activate_counter_q<5>[3:0] -ddr3_controller.delay_before_activate_counter_q<6>[3:0] -ddr3_controller.delay_before_activate_counter_q<7>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_read_counter_q<0>[3:0] -ddr3_controller.delay_before_read_counter_q<1>[3:0] -ddr3_controller.delay_before_read_counter_q<2>[3:0] -ddr3_controller.delay_before_read_counter_q<3>[3:0] -ddr3_controller.delay_before_read_counter_q<4>[3:0] -ddr3_controller.delay_before_read_counter_q<5>[3:0] -ddr3_controller.delay_before_read_counter_q<6>[3:0] -ddr3_controller.delay_before_read_counter_q<7>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_write_counter_q<0>[3:0] -ddr3_controller.delay_before_write_counter_q<1>[3:0] -ddr3_controller.delay_before_write_counter_q<2>[3:0] -ddr3_controller.delay_before_write_counter_q<3>[3:0] -ddr3_controller.delay_before_write_counter_q<4>[3:0] -ddr3_controller.delay_before_write_counter_q<5>[3:0] -ddr3_controller.delay_before_write_counter_q<6>[3:0] -ddr3_controller.delay_before_write_counter_q<7>[3:0] -@200 -- -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/formal_cover_3.gtkw b/formal_cover_3.gtkw deleted file mode 100644 index 8aae927..0000000 --- a/formal_cover_3.gtkw +++ /dev/null @@ -1,1049 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Wed Jun 28 13:01:03 2023 -[*] -[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd" -[dumpfile_mtime] "Wed Jun 28 12:58:52 2023" -[dumpfile_size] 318856 -[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_cover_3.gtkw" -[timestart] 0 -[size] 1848 1126 -[pos] -1 -1 -*-5.617290 175 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] ddr3_controller. -[sst_width] 391 -[signals_width] 350 -[sst_expanded] 1 -[sst_vpaned_height] 743 -@420 -smt_step -@28 -ddr3_controller.i_controller_clk -ddr3_controller.i_rst_n -ddr3_controller.reset_done -@24 -ddr3_controller.state_calibrate[4:0] -ddr3_controller.instruction_address[4:0] -ddr3_controller.delay_counter[15:0] -@200 -- -@28 -ddr3_controller.fifo_1.read_pointer -ddr3_controller.fifo_1.write_pointer -ddr3_controller.wb_properties.i_slave_busy -ddr3_controller.f_read_fifo -@22 -ddr3_controller.f_read_data[616:0] -@c00028 -ddr3_controller.f_write_data[616:0] -@28 -(0)ddr3_controller.f_write_data[616:0] -(1)ddr3_controller.f_write_data[616:0] -(2)ddr3_controller.f_write_data[616:0] -(3)ddr3_controller.f_write_data[616:0] -(4)ddr3_controller.f_write_data[616:0] -(5)ddr3_controller.f_write_data[616:0] -(6)ddr3_controller.f_write_data[616:0] -(7)ddr3_controller.f_write_data[616:0] -(8)ddr3_controller.f_write_data[616:0] -(9)ddr3_controller.f_write_data[616:0] -(10)ddr3_controller.f_write_data[616:0] -(11)ddr3_controller.f_write_data[616:0] -(12)ddr3_controller.f_write_data[616:0] -(13)ddr3_controller.f_write_data[616:0] -(14)ddr3_controller.f_write_data[616:0] -(15)ddr3_controller.f_write_data[616:0] -(16)ddr3_controller.f_write_data[616:0] -(17)ddr3_controller.f_write_data[616:0] -(18)ddr3_controller.f_write_data[616:0] -(19)ddr3_controller.f_write_data[616:0] -(20)ddr3_controller.f_write_data[616:0] -(21)ddr3_controller.f_write_data[616:0] -(22)ddr3_controller.f_write_data[616:0] -(23)ddr3_controller.f_write_data[616:0] -(24)ddr3_controller.f_write_data[616:0] -(25)ddr3_controller.f_write_data[616:0] -(26)ddr3_controller.f_write_data[616:0] -(27)ddr3_controller.f_write_data[616:0] -(28)ddr3_controller.f_write_data[616:0] -(29)ddr3_controller.f_write_data[616:0] -(30)ddr3_controller.f_write_data[616:0] -(31)ddr3_controller.f_write_data[616:0] -(32)ddr3_controller.f_write_data[616:0] -(33)ddr3_controller.f_write_data[616:0] -(34)ddr3_controller.f_write_data[616:0] -(35)ddr3_controller.f_write_data[616:0] -(36)ddr3_controller.f_write_data[616:0] -(37)ddr3_controller.f_write_data[616:0] -(38)ddr3_controller.f_write_data[616:0] -(39)ddr3_controller.f_write_data[616:0] -(40)ddr3_controller.f_write_data[616:0] -(41)ddr3_controller.f_write_data[616:0] -(42)ddr3_controller.f_write_data[616:0] -(43)ddr3_controller.f_write_data[616:0] -(44)ddr3_controller.f_write_data[616:0] -(45)ddr3_controller.f_write_data[616:0] -(46)ddr3_controller.f_write_data[616:0] -(47)ddr3_controller.f_write_data[616:0] -(48)ddr3_controller.f_write_data[616:0] -(49)ddr3_controller.f_write_data[616:0] -(50)ddr3_controller.f_write_data[616:0] -(51)ddr3_controller.f_write_data[616:0] -(52)ddr3_controller.f_write_data[616:0] -(53)ddr3_controller.f_write_data[616:0] -(54)ddr3_controller.f_write_data[616:0] -(55)ddr3_controller.f_write_data[616:0] -(56)ddr3_controller.f_write_data[616:0] -(57)ddr3_controller.f_write_data[616:0] -(58)ddr3_controller.f_write_data[616:0] -(59)ddr3_controller.f_write_data[616:0] -(60)ddr3_controller.f_write_data[616:0] -(61)ddr3_controller.f_write_data[616:0] -(62)ddr3_controller.f_write_data[616:0] -(63)ddr3_controller.f_write_data[616:0] -(64)ddr3_controller.f_write_data[616:0] -(65)ddr3_controller.f_write_data[616:0] -(66)ddr3_controller.f_write_data[616:0] -(67)ddr3_controller.f_write_data[616:0] -(68)ddr3_controller.f_write_data[616:0] -(69)ddr3_controller.f_write_data[616:0] -(70)ddr3_controller.f_write_data[616:0] -(71)ddr3_controller.f_write_data[616:0] -(72)ddr3_controller.f_write_data[616:0] -(73)ddr3_controller.f_write_data[616:0] -(74)ddr3_controller.f_write_data[616:0] -(75)ddr3_controller.f_write_data[616:0] -(76)ddr3_controller.f_write_data[616:0] -(77)ddr3_controller.f_write_data[616:0] -(78)ddr3_controller.f_write_data[616:0] -(79)ddr3_controller.f_write_data[616:0] -(80)ddr3_controller.f_write_data[616:0] -(81)ddr3_controller.f_write_data[616:0] -(82)ddr3_controller.f_write_data[616:0] -(83)ddr3_controller.f_write_data[616:0] -(84)ddr3_controller.f_write_data[616:0] -(85)ddr3_controller.f_write_data[616:0] -(86)ddr3_controller.f_write_data[616:0] -(87)ddr3_controller.f_write_data[616:0] -(88)ddr3_controller.f_write_data[616:0] -(89)ddr3_controller.f_write_data[616:0] -(90)ddr3_controller.f_write_data[616:0] -(91)ddr3_controller.f_write_data[616:0] -(92)ddr3_controller.f_write_data[616:0] -(93)ddr3_controller.f_write_data[616:0] -(94)ddr3_controller.f_write_data[616:0] -(95)ddr3_controller.f_write_data[616:0] -(96)ddr3_controller.f_write_data[616:0] -(97)ddr3_controller.f_write_data[616:0] -(98)ddr3_controller.f_write_data[616:0] -(99)ddr3_controller.f_write_data[616:0] -(100)ddr3_controller.f_write_data[616:0] -(101)ddr3_controller.f_write_data[616:0] -(102)ddr3_controller.f_write_data[616:0] -(103)ddr3_controller.f_write_data[616:0] -(104)ddr3_controller.f_write_data[616:0] -(105)ddr3_controller.f_write_data[616:0] -(106)ddr3_controller.f_write_data[616:0] -(107)ddr3_controller.f_write_data[616:0] -(108)ddr3_controller.f_write_data[616:0] -(109)ddr3_controller.f_write_data[616:0] -(110)ddr3_controller.f_write_data[616:0] -(111)ddr3_controller.f_write_data[616:0] -(112)ddr3_controller.f_write_data[616:0] -(113)ddr3_controller.f_write_data[616:0] -(114)ddr3_controller.f_write_data[616:0] -(115)ddr3_controller.f_write_data[616:0] -(116)ddr3_controller.f_write_data[616:0] -(117)ddr3_controller.f_write_data[616:0] -(118)ddr3_controller.f_write_data[616:0] -(119)ddr3_controller.f_write_data[616:0] -(120)ddr3_controller.f_write_data[616:0] -(121)ddr3_controller.f_write_data[616:0] -(122)ddr3_controller.f_write_data[616:0] -(123)ddr3_controller.f_write_data[616:0] -(124)ddr3_controller.f_write_data[616:0] -(125)ddr3_controller.f_write_data[616:0] -(126)ddr3_controller.f_write_data[616:0] -(127)ddr3_controller.f_write_data[616:0] -(128)ddr3_controller.f_write_data[616:0] -(129)ddr3_controller.f_write_data[616:0] -(130)ddr3_controller.f_write_data[616:0] -(131)ddr3_controller.f_write_data[616:0] -(132)ddr3_controller.f_write_data[616:0] -(133)ddr3_controller.f_write_data[616:0] -(134)ddr3_controller.f_write_data[616:0] -(135)ddr3_controller.f_write_data[616:0] -(136)ddr3_controller.f_write_data[616:0] -(137)ddr3_controller.f_write_data[616:0] -(138)ddr3_controller.f_write_data[616:0] -(139)ddr3_controller.f_write_data[616:0] -(140)ddr3_controller.f_write_data[616:0] -(141)ddr3_controller.f_write_data[616:0] -(142)ddr3_controller.f_write_data[616:0] -(143)ddr3_controller.f_write_data[616:0] -(144)ddr3_controller.f_write_data[616:0] -(145)ddr3_controller.f_write_data[616:0] -(146)ddr3_controller.f_write_data[616:0] -(147)ddr3_controller.f_write_data[616:0] -(148)ddr3_controller.f_write_data[616:0] -(149)ddr3_controller.f_write_data[616:0] -(150)ddr3_controller.f_write_data[616:0] -(151)ddr3_controller.f_write_data[616:0] -(152)ddr3_controller.f_write_data[616:0] -(153)ddr3_controller.f_write_data[616:0] -(154)ddr3_controller.f_write_data[616:0] -(155)ddr3_controller.f_write_data[616:0] -(156)ddr3_controller.f_write_data[616:0] -(157)ddr3_controller.f_write_data[616:0] -(158)ddr3_controller.f_write_data[616:0] -(159)ddr3_controller.f_write_data[616:0] -(160)ddr3_controller.f_write_data[616:0] -(161)ddr3_controller.f_write_data[616:0] -(162)ddr3_controller.f_write_data[616:0] -(163)ddr3_controller.f_write_data[616:0] -(164)ddr3_controller.f_write_data[616:0] -(165)ddr3_controller.f_write_data[616:0] -(166)ddr3_controller.f_write_data[616:0] -(167)ddr3_controller.f_write_data[616:0] -(168)ddr3_controller.f_write_data[616:0] -(169)ddr3_controller.f_write_data[616:0] -(170)ddr3_controller.f_write_data[616:0] -(171)ddr3_controller.f_write_data[616:0] -(172)ddr3_controller.f_write_data[616:0] -(173)ddr3_controller.f_write_data[616:0] -(174)ddr3_controller.f_write_data[616:0] -(175)ddr3_controller.f_write_data[616:0] -(176)ddr3_controller.f_write_data[616:0] -(177)ddr3_controller.f_write_data[616:0] -(178)ddr3_controller.f_write_data[616:0] -(179)ddr3_controller.f_write_data[616:0] -(180)ddr3_controller.f_write_data[616:0] -(181)ddr3_controller.f_write_data[616:0] -(182)ddr3_controller.f_write_data[616:0] -(183)ddr3_controller.f_write_data[616:0] -(184)ddr3_controller.f_write_data[616:0] -(185)ddr3_controller.f_write_data[616:0] -(186)ddr3_controller.f_write_data[616:0] -(187)ddr3_controller.f_write_data[616:0] -(188)ddr3_controller.f_write_data[616:0] -(189)ddr3_controller.f_write_data[616:0] -(190)ddr3_controller.f_write_data[616:0] -(191)ddr3_controller.f_write_data[616:0] -(192)ddr3_controller.f_write_data[616:0] -(193)ddr3_controller.f_write_data[616:0] -(194)ddr3_controller.f_write_data[616:0] -(195)ddr3_controller.f_write_data[616:0] -(196)ddr3_controller.f_write_data[616:0] -(197)ddr3_controller.f_write_data[616:0] -(198)ddr3_controller.f_write_data[616:0] -(199)ddr3_controller.f_write_data[616:0] -(200)ddr3_controller.f_write_data[616:0] -(201)ddr3_controller.f_write_data[616:0] -(202)ddr3_controller.f_write_data[616:0] -(203)ddr3_controller.f_write_data[616:0] -(204)ddr3_controller.f_write_data[616:0] -(205)ddr3_controller.f_write_data[616:0] -(206)ddr3_controller.f_write_data[616:0] -(207)ddr3_controller.f_write_data[616:0] -(208)ddr3_controller.f_write_data[616:0] -(209)ddr3_controller.f_write_data[616:0] -(210)ddr3_controller.f_write_data[616:0] -(211)ddr3_controller.f_write_data[616:0] -(212)ddr3_controller.f_write_data[616:0] -(213)ddr3_controller.f_write_data[616:0] -(214)ddr3_controller.f_write_data[616:0] -(215)ddr3_controller.f_write_data[616:0] -(216)ddr3_controller.f_write_data[616:0] -(217)ddr3_controller.f_write_data[616:0] -(218)ddr3_controller.f_write_data[616:0] -(219)ddr3_controller.f_write_data[616:0] -(220)ddr3_controller.f_write_data[616:0] -(221)ddr3_controller.f_write_data[616:0] -(222)ddr3_controller.f_write_data[616:0] -(223)ddr3_controller.f_write_data[616:0] -(224)ddr3_controller.f_write_data[616:0] -(225)ddr3_controller.f_write_data[616:0] -(226)ddr3_controller.f_write_data[616:0] -(227)ddr3_controller.f_write_data[616:0] -(228)ddr3_controller.f_write_data[616:0] -(229)ddr3_controller.f_write_data[616:0] -(230)ddr3_controller.f_write_data[616:0] -(231)ddr3_controller.f_write_data[616:0] -(232)ddr3_controller.f_write_data[616:0] -(233)ddr3_controller.f_write_data[616:0] -(234)ddr3_controller.f_write_data[616:0] -(235)ddr3_controller.f_write_data[616:0] -(236)ddr3_controller.f_write_data[616:0] -(237)ddr3_controller.f_write_data[616:0] -(238)ddr3_controller.f_write_data[616:0] -(239)ddr3_controller.f_write_data[616:0] -(240)ddr3_controller.f_write_data[616:0] -(241)ddr3_controller.f_write_data[616:0] -(242)ddr3_controller.f_write_data[616:0] -(243)ddr3_controller.f_write_data[616:0] -(244)ddr3_controller.f_write_data[616:0] -(245)ddr3_controller.f_write_data[616:0] -(246)ddr3_controller.f_write_data[616:0] -(247)ddr3_controller.f_write_data[616:0] -(248)ddr3_controller.f_write_data[616:0] -(249)ddr3_controller.f_write_data[616:0] -(250)ddr3_controller.f_write_data[616:0] -(251)ddr3_controller.f_write_data[616:0] -(252)ddr3_controller.f_write_data[616:0] -(253)ddr3_controller.f_write_data[616:0] -(254)ddr3_controller.f_write_data[616:0] -(255)ddr3_controller.f_write_data[616:0] -(256)ddr3_controller.f_write_data[616:0] -(257)ddr3_controller.f_write_data[616:0] -(258)ddr3_controller.f_write_data[616:0] -(259)ddr3_controller.f_write_data[616:0] -(260)ddr3_controller.f_write_data[616:0] -(261)ddr3_controller.f_write_data[616:0] -(262)ddr3_controller.f_write_data[616:0] -(263)ddr3_controller.f_write_data[616:0] -(264)ddr3_controller.f_write_data[616:0] -(265)ddr3_controller.f_write_data[616:0] -(266)ddr3_controller.f_write_data[616:0] -(267)ddr3_controller.f_write_data[616:0] -(268)ddr3_controller.f_write_data[616:0] -(269)ddr3_controller.f_write_data[616:0] -(270)ddr3_controller.f_write_data[616:0] -(271)ddr3_controller.f_write_data[616:0] -(272)ddr3_controller.f_write_data[616:0] -(273)ddr3_controller.f_write_data[616:0] -(274)ddr3_controller.f_write_data[616:0] -(275)ddr3_controller.f_write_data[616:0] -(276)ddr3_controller.f_write_data[616:0] -(277)ddr3_controller.f_write_data[616:0] -(278)ddr3_controller.f_write_data[616:0] -(279)ddr3_controller.f_write_data[616:0] -(280)ddr3_controller.f_write_data[616:0] -(281)ddr3_controller.f_write_data[616:0] -(282)ddr3_controller.f_write_data[616:0] -(283)ddr3_controller.f_write_data[616:0] -(284)ddr3_controller.f_write_data[616:0] -(285)ddr3_controller.f_write_data[616:0] -(286)ddr3_controller.f_write_data[616:0] -(287)ddr3_controller.f_write_data[616:0] -(288)ddr3_controller.f_write_data[616:0] -(289)ddr3_controller.f_write_data[616:0] -(290)ddr3_controller.f_write_data[616:0] -(291)ddr3_controller.f_write_data[616:0] -(292)ddr3_controller.f_write_data[616:0] -(293)ddr3_controller.f_write_data[616:0] -(294)ddr3_controller.f_write_data[616:0] -(295)ddr3_controller.f_write_data[616:0] -(296)ddr3_controller.f_write_data[616:0] -(297)ddr3_controller.f_write_data[616:0] -(298)ddr3_controller.f_write_data[616:0] -(299)ddr3_controller.f_write_data[616:0] -(300)ddr3_controller.f_write_data[616:0] -(301)ddr3_controller.f_write_data[616:0] -(302)ddr3_controller.f_write_data[616:0] -(303)ddr3_controller.f_write_data[616:0] -(304)ddr3_controller.f_write_data[616:0] -(305)ddr3_controller.f_write_data[616:0] -(306)ddr3_controller.f_write_data[616:0] -(307)ddr3_controller.f_write_data[616:0] -(308)ddr3_controller.f_write_data[616:0] -(309)ddr3_controller.f_write_data[616:0] -(310)ddr3_controller.f_write_data[616:0] -(311)ddr3_controller.f_write_data[616:0] -(312)ddr3_controller.f_write_data[616:0] -(313)ddr3_controller.f_write_data[616:0] -(314)ddr3_controller.f_write_data[616:0] -(315)ddr3_controller.f_write_data[616:0] -(316)ddr3_controller.f_write_data[616:0] -(317)ddr3_controller.f_write_data[616:0] -(318)ddr3_controller.f_write_data[616:0] -(319)ddr3_controller.f_write_data[616:0] -(320)ddr3_controller.f_write_data[616:0] -(321)ddr3_controller.f_write_data[616:0] -(322)ddr3_controller.f_write_data[616:0] -(323)ddr3_controller.f_write_data[616:0] -(324)ddr3_controller.f_write_data[616:0] -(325)ddr3_controller.f_write_data[616:0] -(326)ddr3_controller.f_write_data[616:0] -(327)ddr3_controller.f_write_data[616:0] -(328)ddr3_controller.f_write_data[616:0] -(329)ddr3_controller.f_write_data[616:0] -(330)ddr3_controller.f_write_data[616:0] -(331)ddr3_controller.f_write_data[616:0] -(332)ddr3_controller.f_write_data[616:0] -(333)ddr3_controller.f_write_data[616:0] -(334)ddr3_controller.f_write_data[616:0] -(335)ddr3_controller.f_write_data[616:0] -(336)ddr3_controller.f_write_data[616:0] -(337)ddr3_controller.f_write_data[616:0] -(338)ddr3_controller.f_write_data[616:0] -(339)ddr3_controller.f_write_data[616:0] -(340)ddr3_controller.f_write_data[616:0] -(341)ddr3_controller.f_write_data[616:0] -(342)ddr3_controller.f_write_data[616:0] -(343)ddr3_controller.f_write_data[616:0] -(344)ddr3_controller.f_write_data[616:0] -(345)ddr3_controller.f_write_data[616:0] -(346)ddr3_controller.f_write_data[616:0] -(347)ddr3_controller.f_write_data[616:0] -(348)ddr3_controller.f_write_data[616:0] -(349)ddr3_controller.f_write_data[616:0] -(350)ddr3_controller.f_write_data[616:0] -(351)ddr3_controller.f_write_data[616:0] -(352)ddr3_controller.f_write_data[616:0] -(353)ddr3_controller.f_write_data[616:0] -(354)ddr3_controller.f_write_data[616:0] -(355)ddr3_controller.f_write_data[616:0] -(356)ddr3_controller.f_write_data[616:0] -(357)ddr3_controller.f_write_data[616:0] -(358)ddr3_controller.f_write_data[616:0] -(359)ddr3_controller.f_write_data[616:0] -(360)ddr3_controller.f_write_data[616:0] -(361)ddr3_controller.f_write_data[616:0] -(362)ddr3_controller.f_write_data[616:0] -(363)ddr3_controller.f_write_data[616:0] -(364)ddr3_controller.f_write_data[616:0] -(365)ddr3_controller.f_write_data[616:0] -(366)ddr3_controller.f_write_data[616:0] -(367)ddr3_controller.f_write_data[616:0] -(368)ddr3_controller.f_write_data[616:0] -(369)ddr3_controller.f_write_data[616:0] -(370)ddr3_controller.f_write_data[616:0] -(371)ddr3_controller.f_write_data[616:0] -(372)ddr3_controller.f_write_data[616:0] -(373)ddr3_controller.f_write_data[616:0] -(374)ddr3_controller.f_write_data[616:0] -(375)ddr3_controller.f_write_data[616:0] -(376)ddr3_controller.f_write_data[616:0] -(377)ddr3_controller.f_write_data[616:0] -(378)ddr3_controller.f_write_data[616:0] -(379)ddr3_controller.f_write_data[616:0] -(380)ddr3_controller.f_write_data[616:0] -(381)ddr3_controller.f_write_data[616:0] -(382)ddr3_controller.f_write_data[616:0] -(383)ddr3_controller.f_write_data[616:0] -(384)ddr3_controller.f_write_data[616:0] -(385)ddr3_controller.f_write_data[616:0] -(386)ddr3_controller.f_write_data[616:0] -(387)ddr3_controller.f_write_data[616:0] -(388)ddr3_controller.f_write_data[616:0] -(389)ddr3_controller.f_write_data[616:0] -(390)ddr3_controller.f_write_data[616:0] -(391)ddr3_controller.f_write_data[616:0] -(392)ddr3_controller.f_write_data[616:0] -(393)ddr3_controller.f_write_data[616:0] -(394)ddr3_controller.f_write_data[616:0] -(395)ddr3_controller.f_write_data[616:0] -(396)ddr3_controller.f_write_data[616:0] -(397)ddr3_controller.f_write_data[616:0] -(398)ddr3_controller.f_write_data[616:0] -(399)ddr3_controller.f_write_data[616:0] -(400)ddr3_controller.f_write_data[616:0] -(401)ddr3_controller.f_write_data[616:0] -(402)ddr3_controller.f_write_data[616:0] -(403)ddr3_controller.f_write_data[616:0] -(404)ddr3_controller.f_write_data[616:0] -(405)ddr3_controller.f_write_data[616:0] -(406)ddr3_controller.f_write_data[616:0] -(407)ddr3_controller.f_write_data[616:0] -(408)ddr3_controller.f_write_data[616:0] -(409)ddr3_controller.f_write_data[616:0] -(410)ddr3_controller.f_write_data[616:0] -(411)ddr3_controller.f_write_data[616:0] -(412)ddr3_controller.f_write_data[616:0] -(413)ddr3_controller.f_write_data[616:0] -(414)ddr3_controller.f_write_data[616:0] -(415)ddr3_controller.f_write_data[616:0] -(416)ddr3_controller.f_write_data[616:0] -(417)ddr3_controller.f_write_data[616:0] -(418)ddr3_controller.f_write_data[616:0] -(419)ddr3_controller.f_write_data[616:0] -(420)ddr3_controller.f_write_data[616:0] -(421)ddr3_controller.f_write_data[616:0] -(422)ddr3_controller.f_write_data[616:0] -(423)ddr3_controller.f_write_data[616:0] -(424)ddr3_controller.f_write_data[616:0] -(425)ddr3_controller.f_write_data[616:0] -(426)ddr3_controller.f_write_data[616:0] -(427)ddr3_controller.f_write_data[616:0] -(428)ddr3_controller.f_write_data[616:0] -(429)ddr3_controller.f_write_data[616:0] -(430)ddr3_controller.f_write_data[616:0] -(431)ddr3_controller.f_write_data[616:0] -(432)ddr3_controller.f_write_data[616:0] -(433)ddr3_controller.f_write_data[616:0] -(434)ddr3_controller.f_write_data[616:0] -(435)ddr3_controller.f_write_data[616:0] -(436)ddr3_controller.f_write_data[616:0] -(437)ddr3_controller.f_write_data[616:0] -(438)ddr3_controller.f_write_data[616:0] -(439)ddr3_controller.f_write_data[616:0] -(440)ddr3_controller.f_write_data[616:0] -(441)ddr3_controller.f_write_data[616:0] -(442)ddr3_controller.f_write_data[616:0] -(443)ddr3_controller.f_write_data[616:0] -(444)ddr3_controller.f_write_data[616:0] -(445)ddr3_controller.f_write_data[616:0] -(446)ddr3_controller.f_write_data[616:0] -(447)ddr3_controller.f_write_data[616:0] -(448)ddr3_controller.f_write_data[616:0] -(449)ddr3_controller.f_write_data[616:0] -(450)ddr3_controller.f_write_data[616:0] -(451)ddr3_controller.f_write_data[616:0] -(452)ddr3_controller.f_write_data[616:0] -(453)ddr3_controller.f_write_data[616:0] -(454)ddr3_controller.f_write_data[616:0] -(455)ddr3_controller.f_write_data[616:0] -(456)ddr3_controller.f_write_data[616:0] -(457)ddr3_controller.f_write_data[616:0] -(458)ddr3_controller.f_write_data[616:0] -(459)ddr3_controller.f_write_data[616:0] -(460)ddr3_controller.f_write_data[616:0] -(461)ddr3_controller.f_write_data[616:0] -(462)ddr3_controller.f_write_data[616:0] -(463)ddr3_controller.f_write_data[616:0] -(464)ddr3_controller.f_write_data[616:0] -(465)ddr3_controller.f_write_data[616:0] -(466)ddr3_controller.f_write_data[616:0] -(467)ddr3_controller.f_write_data[616:0] -(468)ddr3_controller.f_write_data[616:0] -(469)ddr3_controller.f_write_data[616:0] -(470)ddr3_controller.f_write_data[616:0] -(471)ddr3_controller.f_write_data[616:0] -(472)ddr3_controller.f_write_data[616:0] -(473)ddr3_controller.f_write_data[616:0] -(474)ddr3_controller.f_write_data[616:0] -(475)ddr3_controller.f_write_data[616:0] -(476)ddr3_controller.f_write_data[616:0] -(477)ddr3_controller.f_write_data[616:0] -(478)ddr3_controller.f_write_data[616:0] -(479)ddr3_controller.f_write_data[616:0] -(480)ddr3_controller.f_write_data[616:0] -(481)ddr3_controller.f_write_data[616:0] -(482)ddr3_controller.f_write_data[616:0] -(483)ddr3_controller.f_write_data[616:0] -(484)ddr3_controller.f_write_data[616:0] -(485)ddr3_controller.f_write_data[616:0] -(486)ddr3_controller.f_write_data[616:0] -(487)ddr3_controller.f_write_data[616:0] -(488)ddr3_controller.f_write_data[616:0] -(489)ddr3_controller.f_write_data[616:0] -(490)ddr3_controller.f_write_data[616:0] -(491)ddr3_controller.f_write_data[616:0] -(492)ddr3_controller.f_write_data[616:0] -(493)ddr3_controller.f_write_data[616:0] -(494)ddr3_controller.f_write_data[616:0] -(495)ddr3_controller.f_write_data[616:0] -(496)ddr3_controller.f_write_data[616:0] -(497)ddr3_controller.f_write_data[616:0] -(498)ddr3_controller.f_write_data[616:0] -(499)ddr3_controller.f_write_data[616:0] -(500)ddr3_controller.f_write_data[616:0] -(501)ddr3_controller.f_write_data[616:0] -(502)ddr3_controller.f_write_data[616:0] -(503)ddr3_controller.f_write_data[616:0] -(504)ddr3_controller.f_write_data[616:0] -(505)ddr3_controller.f_write_data[616:0] -(506)ddr3_controller.f_write_data[616:0] -(507)ddr3_controller.f_write_data[616:0] -(508)ddr3_controller.f_write_data[616:0] -(509)ddr3_controller.f_write_data[616:0] -(510)ddr3_controller.f_write_data[616:0] -(511)ddr3_controller.f_write_data[616:0] -(512)ddr3_controller.f_write_data[616:0] -(513)ddr3_controller.f_write_data[616:0] -(514)ddr3_controller.f_write_data[616:0] -(515)ddr3_controller.f_write_data[616:0] -(516)ddr3_controller.f_write_data[616:0] -(517)ddr3_controller.f_write_data[616:0] -(518)ddr3_controller.f_write_data[616:0] -(519)ddr3_controller.f_write_data[616:0] -(520)ddr3_controller.f_write_data[616:0] -(521)ddr3_controller.f_write_data[616:0] -(522)ddr3_controller.f_write_data[616:0] -(523)ddr3_controller.f_write_data[616:0] -(524)ddr3_controller.f_write_data[616:0] -(525)ddr3_controller.f_write_data[616:0] -(526)ddr3_controller.f_write_data[616:0] -(527)ddr3_controller.f_write_data[616:0] -(528)ddr3_controller.f_write_data[616:0] -(529)ddr3_controller.f_write_data[616:0] -(530)ddr3_controller.f_write_data[616:0] -(531)ddr3_controller.f_write_data[616:0] -(532)ddr3_controller.f_write_data[616:0] -(533)ddr3_controller.f_write_data[616:0] -(534)ddr3_controller.f_write_data[616:0] -(535)ddr3_controller.f_write_data[616:0] -(536)ddr3_controller.f_write_data[616:0] -(537)ddr3_controller.f_write_data[616:0] -(538)ddr3_controller.f_write_data[616:0] -(539)ddr3_controller.f_write_data[616:0] -(540)ddr3_controller.f_write_data[616:0] -(541)ddr3_controller.f_write_data[616:0] -(542)ddr3_controller.f_write_data[616:0] -(543)ddr3_controller.f_write_data[616:0] -(544)ddr3_controller.f_write_data[616:0] -(545)ddr3_controller.f_write_data[616:0] -(546)ddr3_controller.f_write_data[616:0] -(547)ddr3_controller.f_write_data[616:0] -(548)ddr3_controller.f_write_data[616:0] -(549)ddr3_controller.f_write_data[616:0] -(550)ddr3_controller.f_write_data[616:0] -(551)ddr3_controller.f_write_data[616:0] -(552)ddr3_controller.f_write_data[616:0] -(553)ddr3_controller.f_write_data[616:0] -(554)ddr3_controller.f_write_data[616:0] -(555)ddr3_controller.f_write_data[616:0] -(556)ddr3_controller.f_write_data[616:0] -(557)ddr3_controller.f_write_data[616:0] -(558)ddr3_controller.f_write_data[616:0] -(559)ddr3_controller.f_write_data[616:0] -(560)ddr3_controller.f_write_data[616:0] -(561)ddr3_controller.f_write_data[616:0] -(562)ddr3_controller.f_write_data[616:0] -(563)ddr3_controller.f_write_data[616:0] -(564)ddr3_controller.f_write_data[616:0] -(565)ddr3_controller.f_write_data[616:0] -(566)ddr3_controller.f_write_data[616:0] -(567)ddr3_controller.f_write_data[616:0] -(568)ddr3_controller.f_write_data[616:0] -(569)ddr3_controller.f_write_data[616:0] -(570)ddr3_controller.f_write_data[616:0] -(571)ddr3_controller.f_write_data[616:0] -(572)ddr3_controller.f_write_data[616:0] -(573)ddr3_controller.f_write_data[616:0] -(574)ddr3_controller.f_write_data[616:0] -(575)ddr3_controller.f_write_data[616:0] -(576)ddr3_controller.f_write_data[616:0] -(577)ddr3_controller.f_write_data[616:0] -(578)ddr3_controller.f_write_data[616:0] -(579)ddr3_controller.f_write_data[616:0] -(580)ddr3_controller.f_write_data[616:0] -(581)ddr3_controller.f_write_data[616:0] -(582)ddr3_controller.f_write_data[616:0] -(583)ddr3_controller.f_write_data[616:0] -(584)ddr3_controller.f_write_data[616:0] -(585)ddr3_controller.f_write_data[616:0] -(586)ddr3_controller.f_write_data[616:0] -(587)ddr3_controller.f_write_data[616:0] -(588)ddr3_controller.f_write_data[616:0] -(589)ddr3_controller.f_write_data[616:0] -(590)ddr3_controller.f_write_data[616:0] -(591)ddr3_controller.f_write_data[616:0] -(592)ddr3_controller.f_write_data[616:0] -(593)ddr3_controller.f_write_data[616:0] -(594)ddr3_controller.f_write_data[616:0] -(595)ddr3_controller.f_write_data[616:0] -(596)ddr3_controller.f_write_data[616:0] -(597)ddr3_controller.f_write_data[616:0] -(598)ddr3_controller.f_write_data[616:0] -(599)ddr3_controller.f_write_data[616:0] -(600)ddr3_controller.f_write_data[616:0] -(601)ddr3_controller.f_write_data[616:0] -(602)ddr3_controller.f_write_data[616:0] -(603)ddr3_controller.f_write_data[616:0] -(604)ddr3_controller.f_write_data[616:0] -(605)ddr3_controller.f_write_data[616:0] -(606)ddr3_controller.f_write_data[616:0] -(607)ddr3_controller.f_write_data[616:0] -(608)ddr3_controller.f_write_data[616:0] -(609)ddr3_controller.f_write_data[616:0] -(610)ddr3_controller.f_write_data[616:0] -(611)ddr3_controller.f_write_data[616:0] -(612)ddr3_controller.f_write_data[616:0] -(613)ddr3_controller.f_write_data[616:0] -(614)ddr3_controller.f_write_data[616:0] -(615)ddr3_controller.f_write_data[616:0] -(616)ddr3_controller.f_write_data[616:0] -@1401200 --group_end -@28 -ddr3_controller.f_write_fifo -ddr3_controller.wb_properties.i_wb_cyc -@24 -ddr3_controller.wb_properties.f_outstanding[3:0] -@28 -ddr3_controller.i_wb_stb -ddr3_controller.o_wb_stall -ddr3_controller.i_wb_cyc -ddr3_controller.o_wb_ack -ddr3_controller.o_wb_stall_d -ddr3_controller.o_wb_stall_q -ddr3_controller.delay_counter_is_zero -@200 -- -@28 -ddr3_controller.stage1_stall -ddr3_controller.stage1_pending -ddr3_controller.stage1_we -@22 -ddr3_controller.stage1_aux[15:0] -@24 -ddr3_controller.stage1_bank[2:0] -@22 -ddr3_controller.stage1_col[9:0] -ddr3_controller.stage1_row[13:0] -@200 -- -@28 -ddr3_controller.stage2_stall -ddr3_controller.stage2_pending -ddr3_controller.stage2_update -ddr3_controller.stage2_we -@c00022 -ddr3_controller.stage2_aux[15:0] -@28 -(0)ddr3_controller.stage2_aux[15:0] -(1)ddr3_controller.stage2_aux[15:0] -(2)ddr3_controller.stage2_aux[15:0] -(3)ddr3_controller.stage2_aux[15:0] -(4)ddr3_controller.stage2_aux[15:0] -(5)ddr3_controller.stage2_aux[15:0] -(6)ddr3_controller.stage2_aux[15:0] -(7)ddr3_controller.stage2_aux[15:0] -(8)ddr3_controller.stage2_aux[15:0] -(9)ddr3_controller.stage2_aux[15:0] -(10)ddr3_controller.stage2_aux[15:0] -(11)ddr3_controller.stage2_aux[15:0] -(12)ddr3_controller.stage2_aux[15:0] -(13)ddr3_controller.stage2_aux[15:0] -(14)ddr3_controller.stage2_aux[15:0] -(15)ddr3_controller.stage2_aux[15:0] -@1401200 --group_end -@24 -ddr3_controller.stage2_bank[2:0] -@22 -ddr3_controller.stage2_col[9:0] -ddr3_controller.stage2_row[13:0] -@200 -- -@28 -+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] -@c00028 -+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0] -@28 -(0)ddr3_controller.cmd_d<1>[23:0] -(1)ddr3_controller.cmd_d<1>[23:0] -(2)ddr3_controller.cmd_d<1>[23:0] -(3)ddr3_controller.cmd_d<1>[23:0] -(4)ddr3_controller.cmd_d<1>[23:0] -(5)ddr3_controller.cmd_d<1>[23:0] -(6)ddr3_controller.cmd_d<1>[23:0] -(7)ddr3_controller.cmd_d<1>[23:0] -(8)ddr3_controller.cmd_d<1>[23:0] -(9)ddr3_controller.cmd_d<1>[23:0] -(10)ddr3_controller.cmd_d<1>[23:0] -(11)ddr3_controller.cmd_d<1>[23:0] -(12)ddr3_controller.cmd_d<1>[23:0] -(13)ddr3_controller.cmd_d<1>[23:0] -(14)ddr3_controller.cmd_d<1>[23:0] -(15)ddr3_controller.cmd_d<1>[23:0] -(16)ddr3_controller.cmd_d<1>[23:0] -(17)ddr3_controller.cmd_d<1>[23:0] -(18)ddr3_controller.cmd_d<1>[23:0] -(19)ddr3_controller.cmd_d<1>[23:0] -(20)ddr3_controller.cmd_d<1>[23:0] -(21)ddr3_controller.cmd_d<1>[23:0] -(22)ddr3_controller.cmd_d<1>[23:0] -(23)ddr3_controller.cmd_d<1>[23:0] -@1401200 --group_end -@c00028 -+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0] -@28 -(0)ddr3_controller.cmd_d<2>[23:0] -(1)ddr3_controller.cmd_d<2>[23:0] -(2)ddr3_controller.cmd_d<2>[23:0] -(3)ddr3_controller.cmd_d<2>[23:0] -(4)ddr3_controller.cmd_d<2>[23:0] -(5)ddr3_controller.cmd_d<2>[23:0] -(6)ddr3_controller.cmd_d<2>[23:0] -(7)ddr3_controller.cmd_d<2>[23:0] -(8)ddr3_controller.cmd_d<2>[23:0] -(9)ddr3_controller.cmd_d<2>[23:0] -(10)ddr3_controller.cmd_d<2>[23:0] -(11)ddr3_controller.cmd_d<2>[23:0] -(12)ddr3_controller.cmd_d<2>[23:0] -(13)ddr3_controller.cmd_d<2>[23:0] -(14)ddr3_controller.cmd_d<2>[23:0] -(15)ddr3_controller.cmd_d<2>[23:0] -(16)ddr3_controller.cmd_d<2>[23:0] -(17)ddr3_controller.cmd_d<2>[23:0] -(18)ddr3_controller.cmd_d<2>[23:0] -(19)ddr3_controller.cmd_d<2>[23:0] -(20)ddr3_controller.cmd_d<2>[23:0] -(21)ddr3_controller.cmd_d<2>[23:0] -(22)ddr3_controller.cmd_d<2>[23:0] -(23)ddr3_controller.cmd_d<2>[23:0] -@1401200 --group_end -@28 -+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] -@200 -- -@24 -ddr3_controller.wb_properties.f_nacks[3:0] -ddr3_controller.wb_properties.f_nreqs[3:0] -ddr3_controller.f_outstanding[3:0] -@23 -ddr3_controller.f_sum_of_pending_acks[31:0] -@200 -- -@28 -ddr3_controller.stage1_pending -ddr3_controller.stage2_pending -ddr3_controller.stage2_update -ddr3_controller.shift_reg_read_pipe_q<4>[16:0] -ddr3_controller.shift_reg_read_pipe_q<3>[16:0] -@c00028 -ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -@28 -(0)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(1)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(2)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(3)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(4)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(5)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(6)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(7)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(8)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(9)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(10)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(11)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(12)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(13)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(14)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(15)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -(16)ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -@1401200 --group_end -@c00028 -ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -@28 -(0)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(1)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(2)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(3)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(4)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(5)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(6)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(7)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(8)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(9)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(10)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(11)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(12)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(13)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(14)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(15)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -(16)ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -@1401200 --group_end -@28 -ddr3_controller.shift_reg_read_pipe_q<0>[16:0] -ddr3_controller.o_wb_ack_read_q<1>[16:0] -ddr3_controller.o_wb_ack_read_q<0>[16:0] -ddr3_controller.o_wb_ack -ddr3_controller.fifo_1.empty -ddr3_controller.fifo_1.full -ddr3_controller.fifo_1.empty -ddr3_controller.fifo_1.full -ddr3_controller.fifo_1.read_fifo -ddr3_controller.fifo_1.write_fifo -ddr3_controller.fifo_1.read_pointer -ddr3_controller.fifo_1.write_pointer -@200 -- -@24 -ddr3_controller.added_read_pipe_max[3:0] -@200 -- -@22 -ddr3_controller.i_aux[15:0] -ddr3_controller.o_aux[15:0] -@200 -- -@22 -ddr3_controller.f_sum_of_pending_acks[31:0] -ddr3_controller.stage1_aux[15:0] -ddr3_controller.stage2_aux[15:0] -ddr3_controller.write_pattern[127:0] -ddr3_controller.read_ack_width[31:0] -ddr3_controller.o_wb_ack_read_q<0>[16:0] -ddr3_controller.o_wb_ack_read_q<1>[16:0] -ddr3_controller.shift_reg_read_pipe_q<0>[16:0] -ddr3_controller.shift_reg_read_pipe_q<1>[16:0] -ddr3_controller.shift_reg_read_pipe_q<2>[16:0] -ddr3_controller.shift_reg_read_pipe_q<3>[16:0] -ddr3_controller.shift_reg_read_pipe_q<4>[16:0] -ddr3_controller.shift_reg_read_pipe_d<0>[16:0] -ddr3_controller.shift_reg_read_pipe_d<1>[16:0] -ddr3_controller.shift_reg_read_pipe_d<2>[16:0] -ddr3_controller.shift_reg_read_pipe_d<3>[16:0] -@200 -- -@28 -ddr3_controller.fifo_1.i_rst_n -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we -@200 -- -@28 -ddr3_controller.o_wb_stall -ddr3_controller.o_wb_stall_d -ddr3_controller.i_wb_cyc -ddr3_controller.i_wb_stb -ddr3_controller.i_wb_we -@24 -ddr3_controller.o_wb_ack -@200 -- -@24 -ddr3_controller.f_activate_slot[1:0] -ddr3_controller.f_precharge_slot[1:0] -ddr3_controller.f_read_slot[1:0] -ddr3_controller.f_write_slot[1:0] -@28 -ddr3_controller.f_read_fifo -ddr3_controller.f_write_fifo -ddr3_controller.i_wb_cyc -ddr3_controller.f_empty -ddr3_controller.fifo_1.empty -ddr3_controller.f_full -ddr3_controller.write_calib_stb -ddr3_controller.write_calib_we -@200 -- -@24 -ddr3_controller.delay_counter[15:0] -ddr3_controller.stage1_bank[2:0] -ddr3_controller.stage2_bank[2:0] -@28 -ddr3_controller.stage1_we -ddr3_controller.stage2_we -ddr3_controller.issue_read_command -ddr3_controller.issue_write_command -@200 -- -@28 -ddr3_controller.bank_status_q[7:0] -@22 -ddr3_controller.delay_before_write_counter_q<1>[3:0] -ddr3_controller.delay_before_read_counter_q<7>[3:0] -ddr3_controller.delay_before_write_counter_q<7>[3:0] -ddr3_controller.delay_before_activate_counter_q<7>[3:0] -ddr3_controller.delay_before_write_counter_q<7>[3:0] -ddr3_controller.delay_before_precharge_counter_q<7>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_activate_counter_q<0>[3:0] -ddr3_controller.delay_before_activate_counter_q<1>[3:0] -ddr3_controller.delay_before_activate_counter_q<2>[3:0] -ddr3_controller.delay_before_activate_counter_q<3>[3:0] -ddr3_controller.delay_before_activate_counter_q<4>[3:0] -ddr3_controller.delay_before_activate_counter_q<5>[3:0] -ddr3_controller.delay_before_activate_counter_q<6>[3:0] -ddr3_controller.delay_before_activate_counter_q<7>[3:0] -ddr3_controller.delay_before_precharge_counter_q<0>[3:0] -ddr3_controller.delay_before_precharge_counter_q<1>[3:0] -ddr3_controller.delay_before_precharge_counter_q<2>[3:0] -ddr3_controller.delay_before_precharge_counter_q<3>[3:0] -ddr3_controller.delay_before_precharge_counter_q<4>[3:0] -ddr3_controller.delay_before_precharge_counter_q<5>[3:0] -ddr3_controller.delay_before_precharge_counter_q<6>[3:0] -ddr3_controller.delay_before_precharge_counter_q<7>[3:0] -ddr3_controller.delay_before_read_counter_q<0>[3:0] -ddr3_controller.delay_before_read_counter_q<1>[3:0] -ddr3_controller.delay_before_read_counter_q<2>[3:0] -ddr3_controller.delay_before_read_counter_q<3>[3:0] -ddr3_controller.delay_before_read_counter_q<4>[3:0] -ddr3_controller.delay_before_read_counter_q<5>[3:0] -ddr3_controller.delay_before_read_counter_q<6>[3:0] -ddr3_controller.delay_before_read_counter_q<7>[3:0] -ddr3_controller.delay_before_write_counter_q<0>[3:0] -ddr3_controller.delay_before_write_counter_q<1>[3:0] -ddr3_controller.delay_before_write_counter_q<2>[3:0] -ddr3_controller.delay_before_write_counter_q<3>[3:0] -ddr3_controller.delay_before_write_counter_q<4>[3:0] -ddr3_controller.delay_before_write_counter_q<5>[3:0] -ddr3_controller.delay_before_write_counter_q<6>[3:0] -ddr3_controller.delay_before_write_counter_q<7>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_activate_counter_q<4>[3:0] -ddr3_controller.delay_before_precharge_counter_q<4>[3:0] -ddr3_controller.delay_before_read_counter_q<4>[3:0] -ddr3_controller.delay_before_write_counter_q<4>[3:0] -@200 -- -@28 -ddr3_controller.cmd_odt -@24 -ddr3_controller.instruction_address[4:0] -@28 -ddr3_controller.stage1_pending -ddr3_controller.stage1_we -ddr3_controller.stage2_pending -ddr3_controller.stage2_we -@24 -ddr3_controller.stage1_bank[2:0] -ddr3_controller.stage2_bank[2:0] -@22 -ddr3_controller.delay_before_write_counter_q<4>[3:0] -ddr3_controller.delay_before_read_counter_q<4>[3:0] -@28 -ddr3_controller.o_wb_stall_d -@24 -ddr3_controller.stage1_col[9:0] -ddr3_controller.stage1_row[13:0] -ddr3_controller.stage2_row[13:0] -ddr3_controller.stage1_next_bank[2:0] -@c00024 -ddr3_controller.stage1_next_row[13:0] -@28 -(0)ddr3_controller.stage1_next_row[13:0] -(1)ddr3_controller.stage1_next_row[13:0] -(2)ddr3_controller.stage1_next_row[13:0] -(3)ddr3_controller.stage1_next_row[13:0] -(4)ddr3_controller.stage1_next_row[13:0] -(5)ddr3_controller.stage1_next_row[13:0] -(6)ddr3_controller.stage1_next_row[13:0] -(7)ddr3_controller.stage1_next_row[13:0] -(8)ddr3_controller.stage1_next_row[13:0] -(9)ddr3_controller.stage1_next_row[13:0] -(10)ddr3_controller.stage1_next_row[13:0] -(11)ddr3_controller.stage1_next_row[13:0] -(12)ddr3_controller.stage1_next_row[13:0] -(13)ddr3_controller.stage1_next_row[13:0] -@1401200 --group_end -@200 -- -@22 -ddr3_controller.delay_before_activate_counter_q<0>[3:0] -ddr3_controller.delay_before_activate_counter_q<1>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_precharge_counter_q<0>[3:0] -ddr3_controller.delay_before_precharge_counter_q<1>[3:0] -@200 -- -@22 -ddr3_controller.delay_before_read_counter_q<0>[3:0] -ddr3_controller.delay_before_read_counter_q<1>[3:0] -@200 -- -@24 -ddr3_controller.bank_active_row_q<0>[13:0] -ddr3_controller.bank_active_row_q<1>[13:0] -ddr3_controller.bank_active_row_q<2>[13:0] -ddr3_controller.bank_active_row_q<3>[13:0] -ddr3_controller.bank_active_row_q<4>[13:0] -ddr3_controller.bank_active_row_q<5>[13:0] -ddr3_controller.bank_active_row_q<6>[13:0] -ddr3_controller.bank_active_row_q<7>[13:0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/formal_test_time.gtkw b/formal_test_time.gtkw deleted file mode 100644 index 941ba8f..0000000 --- a/formal_test_time.gtkw +++ /dev/null @@ -1,278 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Thu Jul 6 11:33:00 2023 -[*] -[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace_induct.vcd" -[dumpfile_mtime] "Thu Jul 6 11:26:58 2023" -[dumpfile_size] 118405 -[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/formal_test_time.gtkw" -[timestart] 0 -[size] 1848 1126 -[pos] -1 -1 -*-4.455849 76 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[treeopen] ddr3_controller. -[sst_width] 391 -[signals_width] 419 -[sst_expanded] 1 -[sst_vpaned_height] 743 -@420 -smt_step -@28 -ddr3_controller.i_controller_clk -ddr3_controller.i_rst_n -ddr3_controller.reset_done -@24 -ddr3_controller.state_calibrate[4:0] -ddr3_controller.instruction_address[4:0] -@28 -ddr3_controller.instruction[27:0] -@24 -ddr3_controller.delay_counter[15:0] -@28 -ddr3_controller.o_wb_stall_q -@29 -ddr3_controller.o_wb_stall_d -@28 -ddr3_controller.o_wb_stall -ddr3_controller.delay_counter_is_zero -ddr3_controller.pause_counter -@200 -- -- -@28 -+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] -@c00028 -+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0] -@28 -(0)ddr3_controller.cmd_d<1>[23:0] -(1)ddr3_controller.cmd_d<1>[23:0] -(2)ddr3_controller.cmd_d<1>[23:0] -(3)ddr3_controller.cmd_d<1>[23:0] -(4)ddr3_controller.cmd_d<1>[23:0] -(5)ddr3_controller.cmd_d<1>[23:0] -(6)ddr3_controller.cmd_d<1>[23:0] -(7)ddr3_controller.cmd_d<1>[23:0] -(8)ddr3_controller.cmd_d<1>[23:0] -(9)ddr3_controller.cmd_d<1>[23:0] -(10)ddr3_controller.cmd_d<1>[23:0] -(11)ddr3_controller.cmd_d<1>[23:0] -(12)ddr3_controller.cmd_d<1>[23:0] -(13)ddr3_controller.cmd_d<1>[23:0] -(14)ddr3_controller.cmd_d<1>[23:0] -(15)ddr3_controller.cmd_d<1>[23:0] -(16)ddr3_controller.cmd_d<1>[23:0] -(17)ddr3_controller.cmd_d<1>[23:0] -(18)ddr3_controller.cmd_d<1>[23:0] -(19)ddr3_controller.cmd_d<1>[23:0] -(20)ddr3_controller.cmd_d<1>[23:0] -(21)ddr3_controller.cmd_d<1>[23:0] -(22)ddr3_controller.cmd_d<1>[23:0] -(23)ddr3_controller.cmd_d<1>[23:0] -@1401200 --group_end -@c00028 -+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0] -@28 -(0)ddr3_controller.cmd_d<2>[23:0] -(1)ddr3_controller.cmd_d<2>[23:0] -(2)ddr3_controller.cmd_d<2>[23:0] -(3)ddr3_controller.cmd_d<2>[23:0] -(4)ddr3_controller.cmd_d<2>[23:0] -(5)ddr3_controller.cmd_d<2>[23:0] -(6)ddr3_controller.cmd_d<2>[23:0] -(7)ddr3_controller.cmd_d<2>[23:0] -(8)ddr3_controller.cmd_d<2>[23:0] -(9)ddr3_controller.cmd_d<2>[23:0] -(10)ddr3_controller.cmd_d<2>[23:0] -(11)ddr3_controller.cmd_d<2>[23:0] -(12)ddr3_controller.cmd_d<2>[23:0] -(13)ddr3_controller.cmd_d<2>[23:0] -(14)ddr3_controller.cmd_d<2>[23:0] -(15)ddr3_controller.cmd_d<2>[23:0] -(16)ddr3_controller.cmd_d<2>[23:0] -(17)ddr3_controller.cmd_d<2>[23:0] -(18)ddr3_controller.cmd_d<2>[23:0] -(19)ddr3_controller.cmd_d<2>[23:0] -(20)ddr3_controller.cmd_d<2>[23:0] -(21)ddr3_controller.cmd_d<2>[23:0] -(22)ddr3_controller.cmd_d<2>[23:0] -(23)ddr3_controller.cmd_d<2>[23:0] -@1401200 --group_end -@28 -+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] -@200 -- -@28 -ddr3_controller.bank_status_q[7:0] -@200 -- -@28 -ddr3_controller.stage1_pending -ddr3_controller.stage2_pending -ddr3_controller.stage2_update -@200 -- -@24 -ddr3_controller.bank_const[2:0] -ddr3_controller.f_timer[6:0] -ddr3_controller.f_activate_time_stamp<0>[6:0] -ddr3_controller.f_activate_time_stamp<1>[6:0] -ddr3_controller.f_activate_time_stamp<2>[6:0] -ddr3_controller.f_activate_time_stamp<3>[6:0] -ddr3_controller.f_activate_time_stamp<4>[6:0] -ddr3_controller.f_activate_time_stamp<5>[6:0] -ddr3_controller.f_activate_time_stamp<6>[6:0] -ddr3_controller.f_activate_time_stamp<7>[6:0] -@22 -ddr3_controller.delay_before_precharge_counter_q<0>[3:0] -@24 -ddr3_controller.f_precharge_time_stamp<0>[6:0] -@22 -ddr3_controller.f_precharge_time_stamp<1>[6:0] -ddr3_controller.f_precharge_time_stamp<2>[6:0] -ddr3_controller.f_precharge_time_stamp<3>[6:0] -ddr3_controller.f_precharge_time_stamp<4>[6:0] -ddr3_controller.f_precharge_time_stamp<5>[6:0] -ddr3_controller.f_precharge_time_stamp<6>[6:0] -ddr3_controller.f_precharge_time_stamp<7>[6:0] -@24 -ddr3_controller.f_read_time_stamp<0>[6:0] -ddr3_controller.f_read_time_stamp<1>[6:0] -ddr3_controller.f_read_time_stamp<2>[6:0] -ddr3_controller.f_read_time_stamp<3>[6:0] -ddr3_controller.f_read_time_stamp<4>[6:0] -ddr3_controller.f_read_time_stamp<5>[6:0] -ddr3_controller.f_read_time_stamp<6>[6:0] -ddr3_controller.f_read_time_stamp<7>[6:0] -ddr3_controller.f_write_time_stamp<0>[6:0] -ddr3_controller.f_write_time_stamp<1>[6:0] -ddr3_controller.f_write_time_stamp<2>[6:0] -ddr3_controller.f_write_time_stamp<3>[6:0] -ddr3_controller.f_write_time_stamp<4>[6:0] -ddr3_controller.f_write_time_stamp<5>[6:0] -ddr3_controller.f_write_time_stamp<6>[6:0] -ddr3_controller.f_write_time_stamp<7>[6:0] -@28 -ddr3_controller.i_wb_stb -ddr3_controller.o_wb_stall -ddr3_controller.i_wb_cyc -ddr3_controller.o_wb_ack -ddr3_controller.o_wb_stall_d -ddr3_controller.o_wb_stall_q -ddr3_controller.delay_counter_is_zero -@200 -- -@28 -ddr3_controller.stage1_stall -ddr3_controller.stage1_pending -ddr3_controller.stage1_we -@22 -ddr3_controller.stage1_aux[15:0] -@24 -ddr3_controller.stage1_bank[2:0] -@22 -ddr3_controller.stage1_col[9:0] -ddr3_controller.stage1_row[13:0] -@200 -- -@28 -ddr3_controller.stage2_stall -ddr3_controller.stage2_pending -ddr3_controller.stage2_update -ddr3_controller.stage2_we -@c00022 -ddr3_controller.stage2_aux[15:0] -@28 -(0)ddr3_controller.stage2_aux[15:0] -(1)ddr3_controller.stage2_aux[15:0] -(2)ddr3_controller.stage2_aux[15:0] -(3)ddr3_controller.stage2_aux[15:0] -(4)ddr3_controller.stage2_aux[15:0] -(5)ddr3_controller.stage2_aux[15:0] -(6)ddr3_controller.stage2_aux[15:0] -(7)ddr3_controller.stage2_aux[15:0] -(8)ddr3_controller.stage2_aux[15:0] -(9)ddr3_controller.stage2_aux[15:0] -(10)ddr3_controller.stage2_aux[15:0] -(11)ddr3_controller.stage2_aux[15:0] -(12)ddr3_controller.stage2_aux[15:0] -(13)ddr3_controller.stage2_aux[15:0] -(14)ddr3_controller.stage2_aux[15:0] -(15)ddr3_controller.stage2_aux[15:0] -@1401200 --group_end -@24 -ddr3_controller.stage2_bank[2:0] -@22 -ddr3_controller.stage2_col[9:0] -ddr3_controller.stage2_row[13:0] -@200 -- -@28 -+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] -@c00028 -+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0] -@28 -(0)ddr3_controller.cmd_d<1>[23:0] -(1)ddr3_controller.cmd_d<1>[23:0] -(2)ddr3_controller.cmd_d<1>[23:0] -(3)ddr3_controller.cmd_d<1>[23:0] -(4)ddr3_controller.cmd_d<1>[23:0] -(5)ddr3_controller.cmd_d<1>[23:0] -(6)ddr3_controller.cmd_d<1>[23:0] -(7)ddr3_controller.cmd_d<1>[23:0] -(8)ddr3_controller.cmd_d<1>[23:0] -(9)ddr3_controller.cmd_d<1>[23:0] -(10)ddr3_controller.cmd_d<1>[23:0] -(11)ddr3_controller.cmd_d<1>[23:0] -(12)ddr3_controller.cmd_d<1>[23:0] -(13)ddr3_controller.cmd_d<1>[23:0] -(14)ddr3_controller.cmd_d<1>[23:0] -(15)ddr3_controller.cmd_d<1>[23:0] -(16)ddr3_controller.cmd_d<1>[23:0] -(17)ddr3_controller.cmd_d<1>[23:0] -(18)ddr3_controller.cmd_d<1>[23:0] -(19)ddr3_controller.cmd_d<1>[23:0] -(20)ddr3_controller.cmd_d<1>[23:0] -(21)ddr3_controller.cmd_d<1>[23:0] -(22)ddr3_controller.cmd_d<1>[23:0] -(23)ddr3_controller.cmd_d<1>[23:0] -@1401200 --group_end -@c00028 -+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0] -@28 -(0)ddr3_controller.cmd_d<2>[23:0] -(1)ddr3_controller.cmd_d<2>[23:0] -(2)ddr3_controller.cmd_d<2>[23:0] -(3)ddr3_controller.cmd_d<2>[23:0] -(4)ddr3_controller.cmd_d<2>[23:0] -(5)ddr3_controller.cmd_d<2>[23:0] -(6)ddr3_controller.cmd_d<2>[23:0] -(7)ddr3_controller.cmd_d<2>[23:0] -(8)ddr3_controller.cmd_d<2>[23:0] -(9)ddr3_controller.cmd_d<2>[23:0] -(10)ddr3_controller.cmd_d<2>[23:0] -(11)ddr3_controller.cmd_d<2>[23:0] -(12)ddr3_controller.cmd_d<2>[23:0] -(13)ddr3_controller.cmd_d<2>[23:0] -(14)ddr3_controller.cmd_d<2>[23:0] -(15)ddr3_controller.cmd_d<2>[23:0] -(16)ddr3_controller.cmd_d<2>[23:0] -(17)ddr3_controller.cmd_d<2>[23:0] -(18)ddr3_controller.cmd_d<2>[23:0] -(19)ddr3_controller.cmd_d<2>[23:0] -(20)ddr3_controller.cmd_d<2>[23:0] -(21)ddr3_controller.cmd_d<2>[23:0] -(22)ddr3_controller.cmd_d<2>[23:0] -(23)ddr3_controller.cmd_d<2>[23:0] -@1401200 --group_end -@28 -+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] -@200 -- -- -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/log_regression_test.log b/log_regression_test.log deleted file mode 100644 index db671db..0000000 --- a/log_regression_test.log +++ /dev/null @@ -1,106 +0,0 @@ -BUS_DELAY: 0 ps -FLY_BY_DELAY: 0 ps -Log File: sim_busdelay0_flybydelay0.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 250810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:16 ; elapsed = 00:47:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1332 ; free virtual = 24744 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2805770 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 14:58:39 2023... - - -BUS_DELAY: 625 ps -FLY_BY_DELAY: 0 ps -Log File: sim_busdelay625_flybydelay0.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 234810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:15 ; elapsed = 00:44:56 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1358 ; free virtual = 24780 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2640970 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 15:46:48 2023... - - -BUS_DELAY: 1250 ps -FLY_BY_DELAY: 600 ps -Log File: sim_busdelay1250_flybydelay600.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 284 us : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:17 ; elapsed = 00:53:20 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1238 ; free virtual = 24677 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147150 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 16:43:17 2023... - - -BUS_DELAY: 1875 ps -FLY_BY_DELAY: 1000 ps -Log File: sim_busdelay1875_flybydelay1000.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 261610 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:17 ; elapsed = 00:57:38 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 174 ; free virtual = 23702 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2965430 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 17:44:52 2023... - - -BUS_DELAY: 2500 ps -FLY_BY_DELAY: 1500 ps -Log File: sim_busdelay2500_flybydelay1500.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 277970 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:18 ; elapsed = 00:59:53 . Memory (MB): peak = 2833.148 ; gain = 476.559 ; free physical = 1580 ; free virtual = 24408 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147790 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 18:48:36 2023... - - -BUS_DELAY: 5000 ps -FLY_BY_DELAY: 2200 ps -Log File: sim_busdelay5000_flybydelay2200.log -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 273380 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:16 ; elapsed = 00:52:07 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1814 ; free virtual = 24675 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3030440 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 19:44:03 2023... - - -BUS_DELAY: 10000 ps -FLY_BY_DELAY: 3000 ps -Log File: sim_busdelay10000_flybydelay3000.log - diff --git a/model.log b/model.log deleted file mode 100644 index b9f4d01..0000000 --- a/model.log +++ /dev/null @@ -1,32553 +0,0 @@ -relaunch_sim -INFO: xsimkernel Simulation Memory Usage: 235040 KB (Peak: 292836 KB), Simulation CPU Usage: 480920 ms -Command: launch_simulation -step compile -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-2] XSim::Compile design -INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xvlog --incr --relax -L uvm -prj ddr3_dimm_micron_sim_vlog.prj -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2458] undeclared symbol TZQCS, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:549] -INFO: [VRFC 10-2458] undeclared symbol TZQINIT, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:550] -INFO: [VRFC 10-2458] undeclared symbol TZQOPER, assumed default net type wire [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3.v:551] -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Waiting for jobs to finish... -No pending jobs, compilation finished. -INFO: [USF-XSim-69] 'compile' step finished in '3' seconds -Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-3] XSim::Elaborate design -INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Using 8 slave threads. -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:172] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:103] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:124] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:125] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:126] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:127] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:128] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:129] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:131] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:133] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:218] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:246] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:247] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:248] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:252] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:254] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:290] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:291] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:295] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:296] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:297] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:349] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:350] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:396] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:397] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:398] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:400] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:402] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:404] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:434] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:473] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:474] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:478] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:479] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:480] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:528] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:529] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:597] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:598] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v:644] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:151] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:152] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:153] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:154] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:159] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:160] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:162] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/imports/DDR3 SDRAM Verilog Model/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v:149] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_controller.v" Line 27. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_controller.v" Line 27. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sources_1/imports/DDR3/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim_behav -run_program: Time (s): cpu = 00:02:40 ; elapsed = 00:01:38 . Memory (MB): peak = 10214.414 ; gain = 0.000 ; free physical = 1336 ; free virtual = 23265 -INFO: [USF-XSim-69] 'elaborate' step finished in '97' seconds -launch_simulation: Time (s): cpu = 00:02:40 ; elapsed = 00:01:38 . Memory (MB): peak = 10214.414 ; gain = 0.000 ; free physical = 1336 ; free virtual = 23265 -Time resolution is 1 ps -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file: at time 0 INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U1.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U2.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U3.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U4.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U6.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U7.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U8.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.0. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.1. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.2. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.3. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.4. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.5. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.6. -ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file: at time 0.0 ps INFO: opening /tmp/ddr3_dimm_micron_sim.ddr3_dimm.U9.open_bank_file.7. -ddr3_dimm_micron_sim.ddr3_dimm: Single Rank -ddr3_dimm_micron_sim.ddr3_dimm: non ECC -ddr3_dimm_micron_sim.ddr3_dimm: Unbuffered DIMM -ddr3_dimm_micron_sim.ddr3_dimm: Component Width = x8 -ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 291400.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 803300.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -run: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 10217.297 ; gain = 0.000 ; free physical = 1219 ; free virtual = 23150 -relaunch_xsim_kernel: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 10217.297 ; gain = 2.883 ; free physical = 1219 ; free virtual = 23150 -relaunch_sim: Time (s): cpu = 00:10:43 ; elapsed = 00:01:52 . Memory (MB): peak = 10217.297 ; gain = 2.883 ; free physical = 1219 ; free virtual = 23150 -run all -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Partial Array Self Refresh = Bank 0-7 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 CAS Write Latency = 5 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Auto Self Refresh = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Self Refresh Temperature = Normal -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1175800.0 ps INFO: Load Mode 2 Dynamic ODT = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1195800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Length = 8 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Burst Order = Sequential -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 CAS Latency = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 DLL Reset = Reset DLL -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Write Recovery = 7 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1205800.0 ps INFO: Load Mode 0 Power Down Mode = DLL off -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1255800.0 ps INFO: ZQ long = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1255800.0 ps INFO: Initialization Sequence is complete -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2545800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2575800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 2888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd= , prev_time=x ps, difference=x ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 2910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=2888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3758300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3638300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3772050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3773300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3774550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3775800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3777050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3778300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3779550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3780800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 3888300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3758300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3902050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3903300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3904550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3905800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3907050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3908300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3909550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 3910800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4008300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=3888300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4022050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4023300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4024550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4025800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4027050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4028300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4029550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4030800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4138300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4008300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4152050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4153300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4154550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4155800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4157050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4158300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4159550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4160800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4258300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4138300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4272050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4273300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4274550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4275800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4277050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4278300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4279550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4280800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4388300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4258300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4402050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4403300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4404550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4405800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4407050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4408300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4409550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4410800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4388300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4638300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4508300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4652050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4653300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4654550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4655800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4657050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4658300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4659550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4660800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4768300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4638300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4782050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4783300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4784550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4785800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4787050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4788300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4789550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4790800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 4898300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4768300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4912050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4913300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4914550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4915800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4917050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4918300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4919550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 4920800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=4898300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5378300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 5890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 5998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=5998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6368300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6248300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6382050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6383300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6384550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6385800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6387050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6388300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6389550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6390800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6498300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6368300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6512050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6513300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6514550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6515800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6517050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6518300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6519550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6520800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6618300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6498300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6632050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6633300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6634550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6635800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6637050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6638300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6639550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6640800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6748300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6618300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6762050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6763300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6764550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6765800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6767050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6768300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6769550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6770800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6868300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6748300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6882050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6883300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6884550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6885800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6887050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6888300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6889550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 6890800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 6998300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6868300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7012050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7013300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7014550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7015800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7017050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7018300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7019550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7020800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=6998300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7248300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7118300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7262050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7263300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7264550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7265800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7267050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7268300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7269550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7270800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7378300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7248300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7392050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7393300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7394550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7395800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7397050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7398300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7399550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7400800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7508300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7378300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7522050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7523300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7524550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7525800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7527050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7528300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7529550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 7530800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 7988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7508300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=7988300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 8978300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8858300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8992050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8993300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8994550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8995800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8997050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8998300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 8999550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9000800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9108300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=8978300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9122050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9123300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9124550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9125800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9127050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9128300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9129550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9130800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9228300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9108300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9242050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9243300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9244550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9245800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9247050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9248300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9249550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9250800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9358300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9228300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9372050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9373300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9374550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9375800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9377050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9378300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9379550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9380800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9478300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9358300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9492050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9493300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9494550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9495800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9497050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9498300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9499550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9500800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9608300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9478300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9622050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9623300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9624550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9625800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9627050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9628300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9629550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9630800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9608300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9858300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9728300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9872050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9873300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9874550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9875800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9877050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9878300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9879550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 9880800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 9988300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9858300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10002050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10003300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10004550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10005800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10007050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10008300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10009550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10010800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10118300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=9988300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10132050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10133300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10134550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10135800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10137050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10138300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10139550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10140800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10118300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10598300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 10968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 10990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=10968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11588300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11468300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11602050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11603300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11604550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11605800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11607050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11608300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11609550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11610800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11718300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11588300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11732050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11733300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11734550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11735800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11737050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11738300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11739550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11740800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11838300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11718300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11852050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11853300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11854550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11855800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11857050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11858300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11859550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11860800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 11968300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11838300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11982050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11983300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11984550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11985800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11987050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11988300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11989550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 11990800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12088300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=11968300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12102050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12103300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12104550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12105800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12107050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12108300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12109550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12110800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12218300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12088300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12232050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12233300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12234550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12235800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12237050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12238300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12239550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12240800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12218300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12468300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12338300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12482050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12483300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12484550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12485800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12487050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12488300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12489550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12490800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12598300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12468300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12612050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12613300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12614550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12615800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12617050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12618300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12619550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12620800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 12728300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12598300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12742050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12743300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12744550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12745800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12747050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12748300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12749550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 12750800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=12728300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13208300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 13948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 13970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=13948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14198300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14078300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14212050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14213300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14214550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14215800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14217050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14218300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14219550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14220800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14328300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14198300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14342050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14343300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14344550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14345800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14347050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14348300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14349550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14350800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14448300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14328300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14462050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14463300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14464550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14465800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14467050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14468300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14469550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14470800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14578300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14448300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14592050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14593300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14594550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14595800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14597050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14598300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14599550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14600800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14698300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14578300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14712050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14713300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14714550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14715800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14717050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14718300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14719550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14720800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14828300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14698300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14842050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14843300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14844550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14845800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14847050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14848300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14849550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14850800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 14948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14828300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 14970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15078300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=14948300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15092050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15093300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15094550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15095800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15097050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15098300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15099550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15100800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15208300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15078300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15222050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15223300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15224550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15225800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15227050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15228300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15229550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15230800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15338300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15208300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15352050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15353300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15354550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15355800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15357050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15358300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15359550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15360800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15338300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 15938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15818300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 15960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=15938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16808300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16688300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16822050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16823300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16824550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16825800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16827050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16828300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16829550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16830800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 16938300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16808300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16952050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16953300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16954550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16955800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16957050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16958300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16959550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 16960800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17058300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=16938300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17072050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17073300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17074550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17075800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17077050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17078300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17079550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17080800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17188300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17058300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17202050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17203300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17204550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17205800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17207050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17208300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17209550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17210800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17308300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17188300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17322050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17323300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17324550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17325800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17327050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17328300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17329550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17330800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17438300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17308300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17452050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17453300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17454550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17455800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17457050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17458300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17459550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17460800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17438300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17688300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17558300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17702050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17703300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17704550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17705800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17707050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17708300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17709550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17710800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17818300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17688300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17832050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17833300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17834550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17835800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17837050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17838300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17839550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17840800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 17948300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17818300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17962050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17963300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17964550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17965800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17967050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17968300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17969550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 17970800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=17948300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18428300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 18918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 18940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=18918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19418300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19298300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19432050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19433300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19434550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19435800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19437050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19438300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19439550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19440800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19548300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19418300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19562050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19563300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19564550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19565800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19567050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19568300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19569550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19570800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19668300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19548300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19682050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19683300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19684550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19685800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19687050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19688300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19689550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19690800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19798300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19668300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19812050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19813300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19814550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19815800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19817050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19818300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19819550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19820800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 19918300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19798300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19932050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19933300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19934550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19935800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19937050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19938300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19939550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 19940800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20048300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=19918300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20062050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20063300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20064550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20065800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20067050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20068300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20069550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20070800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20048300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20298300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20168300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20312050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20313300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20314550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20315800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20317050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20318300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20319550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20320800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20428300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20298300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20442050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20443300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20444550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20445800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20447050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20448300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20449550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20450800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 20558300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20428300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20572050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20573300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20574550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20575800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20577050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20578300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20579550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 20580800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=20558300 ps, difference=480000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21038300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 21908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 21930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22028300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=21908300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22042050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22043300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22044550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22045800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22047050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22048300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22049550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22050800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22158300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22028300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22172050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22173300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22174550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22175800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22177050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22178300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22179550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22180800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22158300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22292050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22293300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22294550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22295800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22297050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22298300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22299550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22300800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22408300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22278300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22422050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22423300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22424550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22425800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22427050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22428300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22429550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22430800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22528300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22408300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22542050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22543300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22544550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22545800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22547050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22548300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22549550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22550800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22658300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22528300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22672050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22673300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22674550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22675800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22677050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22678300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22679550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22680800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22778300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22658300 ps, difference=120000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22792050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22793300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22794550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22795800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22797050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22798300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22799550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22800800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 22908300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22778300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22922050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22923300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22924550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22925800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22927050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22928300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22929550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 22930800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23038300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=22908300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23052050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23053300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23054550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23055800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23057050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23058300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23059550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23060800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23168300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=23038300 ps, difference=130000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23182050.0 ps READ @ DQS MultiPurpose Register 0, col = 0, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23183300.0 ps READ @ DQS MultiPurpose Register 0, col = 1, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23184550.0 ps READ @ DQS MultiPurpose Register 0, col = 2, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23185800.0 ps READ @ DQS MultiPurpose Register 0, col = 3, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23187050.0 ps READ @ DQS MultiPurpose Register 0, col = 4, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23188300.0 ps READ @ DQS MultiPurpose Register 0, col = 5, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23189550.0 ps READ @ DQS MultiPurpose Register 0, col = 6, data = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 23190800.0 ps READ @ DQS MultiPurpose Register 0, col = 7, data = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Select = Pre-defined pattern -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23405800.0 ps INFO: Load Mode 3 MultiPurpose Register Enable = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Write Levelization = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 23415800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 23550800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23701502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23704002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23706502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23709002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23711502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23714002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23716502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23719002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23851580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23854080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23856580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23859080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23861580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23864080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23866580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 23868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 23869080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24001658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24004158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24006658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24009158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24011658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24014158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24016658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24019158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24151736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24154236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24156736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24159236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24161736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24164236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24166736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24169236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24301814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24304314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24306814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24309314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24311814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24314314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24316814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24319314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24451892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24452050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24454392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24454550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24456892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24457050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24459392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24459550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24461892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24462050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24464392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24464550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24466892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24467050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24469392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24469550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24601970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24602050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24604470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24604550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24606970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24607050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24609470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24609550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24611970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24612050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24614470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24614550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24616970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24617050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24619470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24619550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24752048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24752050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24754548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24754550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24757048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24757050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24759548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24759550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24762048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24762050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24764548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24764550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24767048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24767050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24769548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 24769550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24902126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24902126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24904626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24904626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24907126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24907126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24909626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24909626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24912126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24912126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24914626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24914626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24917126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24917126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 24918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24919626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 24919626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25052204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25052204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25054704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25054704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25057204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25057204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25059704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25059704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25062204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25062204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25064704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25064704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25067204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25067204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25069704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25069704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25202282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25204782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25207282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25209782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25212282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25214782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25217282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25219782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25352360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25354860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25357360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25359860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25362360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25364860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25367360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25369860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25502438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25504938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25507438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25509938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25512438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25514938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25517438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25519938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25652516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25655016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25657516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25660016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25662516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25665016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25667516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25670016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25802594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25805094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25807594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25810094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25812594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25815094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25817594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25820094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25952672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25955172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25957672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25960172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25962672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25965172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25967672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 25968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 25970172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26102750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26105250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26107750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26110250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26112750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26115250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26117750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26120250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26252828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26255328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26257828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26260328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26262828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26265328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26267828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26270328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26402906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26405406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26407906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26410406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26412906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26415406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26417906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26420406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26552984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26555484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26557984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26560484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26562984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26565484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26567984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26570484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26703062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26705562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26708062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26710562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26713062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26715562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26718062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26720562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26853140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26853300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26855640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26855800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26858140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26858300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26860640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26860800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26863140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26863300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26865640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26865800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26868140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26868300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 26868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 26870640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 26870800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27003218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27003300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27005718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27005800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27008218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27008300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27010718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27010800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27013218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27013300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27015718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27015800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27018218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27018300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27020718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27020800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27150800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27150800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27153300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27153300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27155800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27155800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27158300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27158300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27160800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27160800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27163300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27163300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27165800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27165800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27168300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27168300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27601502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27604002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27606502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27609002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27611502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27614002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27616502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27619002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27751580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27754080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27756580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27759080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27761580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27764080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27766580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27769080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27901658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27904158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27906658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27909158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27911658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27914158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27916658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 27918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 27919158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28051736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28054236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28056736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28059236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28061736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28064236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28066736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28069236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28201814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28204314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28206814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28209314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28211814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28214314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28216814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28219314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28351892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28352050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28354392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28354550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28356892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28357050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28359392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28359550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28361892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28362050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28364392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28364550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28366892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28367050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28369392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28369550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28501970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28502050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28504470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28504550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28506970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28507050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28509470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28509550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28511970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28512050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28514470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28514550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28516970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28517050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28519470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28519550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28652048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28652050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28654548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28654550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28657048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28657050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28659548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28659550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28662048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28662050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28664548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28664550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28667048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28667050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28669548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28669550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28802126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28802126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28804626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28804626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28807126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28807126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28809626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28809626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28812126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28812126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28814626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28814626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28817126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28817126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28819626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28819626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28952204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28952204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28954704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28954704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28957204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28957204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28959704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28959704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28962204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28962204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28964704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28964704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28967204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28967204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 28968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 28968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28969704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 28969704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29102282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29104782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29107282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29109782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29112282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29114782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29117282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29119782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29252360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29254860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29257360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29259860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29262360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29264860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29267360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29269860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29402438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29404938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29407438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29409938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29412438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29414938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29417438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29419938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29552516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29555016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29557516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29560016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29562516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29565016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29567516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29570016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29702594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29705094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29707594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29710094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29712594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29715094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29717594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29720094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29852672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29855172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29857672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29860172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29862672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29865172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29867672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 29868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 29870172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30002750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30005250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30007750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30010250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30012750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30015250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30017750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30020250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30152828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30155328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30157828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30160328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30162828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30165328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30167828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30170328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30302906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30305406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30307906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30310406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30312906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30315406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30317906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30320406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30452984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30455484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30457984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30460484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30462984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30465484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30467984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30470484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30603062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30605562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30608062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30610562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30613062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30615562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30618062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30620562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30753140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30753300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30755640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30755800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30758140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30758300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30760640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30760800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30763140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30763300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30765640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30765800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30768140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30768300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30770640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30770800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30903218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30903300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30905718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30905800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30908218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30908300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30910718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30910800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30913218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30913300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30915718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30915800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30918218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30918300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 30918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30920718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30920800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31050800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31050800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31053300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31053300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31055800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31055800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31058300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31058300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31060800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31060800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31063300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31063300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31065800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31065800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31068300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 31068300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31501502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31504002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31506502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31509002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31511502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31514002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31516502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31519002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31651580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31654080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31656580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31659080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31661580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31664080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31666580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31669080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31801658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31804158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31806658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31809158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31811658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31814158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31816658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31819158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31951736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31954236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31956736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31959236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31961736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31964236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31966736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 31968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 31968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 31969236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32101814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32104314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32106814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32109314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32111814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32114314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32116814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32119314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32251892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32252050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32254392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32254550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32256892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32257050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32259392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32259550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32261892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32262050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32264392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32264550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32266892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32267050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32269392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32269550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32401970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32402050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32404470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32404550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32406970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32407050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32409470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32409550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32411970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32412050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32414470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32414550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32416970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32417050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32419470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32419550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32552048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32552050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32554548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32554550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32557048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32557050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32559548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32559550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32562048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32562050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32564548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32564550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32567048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32567050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32569548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32569550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32702126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32702126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32704626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32704626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32707126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32707126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32709626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32709626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32712126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32712126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32714626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32714626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32717126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32717126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32719626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32719626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32852204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32852204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32854704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32854704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32857204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32857204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32859704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32859704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32862204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32862204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32864704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32864704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32867204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32867204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 32868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32869704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 32869704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33002282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33004782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33007282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33009782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33012282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33014782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33017282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33019782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33152360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33154860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33157360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33159860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33162360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33164860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33167360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33169860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33302438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33304938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33307438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33309938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33312438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33314938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33317438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33319938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33452516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33455016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33457516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33460016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33462516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33465016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33467516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33470016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33602594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33605094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33607594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33610094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33612594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33615094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33617594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33620094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33752672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33755172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33757672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33760172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33762672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33765172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33767672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33770172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33902750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33905250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33907750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33910250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33912750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33915250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33917750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 33918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33920250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34052828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34055328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34057828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34060328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34062828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34065328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34067828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34070328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34202906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34205406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34207906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34210406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34212906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34215406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34217906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34220406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34352984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34355484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34357984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34360484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34362984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34365484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34367984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34370484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34503062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34505562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34508062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34510562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34513062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34515562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34518062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34520562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34653140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34653300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34655640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34655800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34658140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34658300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34660640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34660800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34663140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34663300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34665640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34665800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34668140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34668300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34670640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34670800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34803218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34803300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34805718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34805800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34808218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34808300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34810718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34810800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34813218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34813300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34815718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34815800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34818218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34818300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34820718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34820800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34950800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34950800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34953300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34953300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34955800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34955800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34958300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34958300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34960800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34960800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34963300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34963300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34965800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34965800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 34968300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 34968300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 34968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35401502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35404002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35406502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35409002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35411502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35414002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35416502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35419002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35551580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35554080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35556580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35559080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35561580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35564080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35566580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35569080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35701658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35704158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35706658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35709158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35711658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35714158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35716658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35719158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35851736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35854236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35856736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35859236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35861736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35864236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35866736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 35868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 35869236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36001814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36004314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36006814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36009314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36011814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36014314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36016814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36019314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36151892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36152050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36154392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36154550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36156892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36157050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36159392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36159550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36161892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36162050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36164392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36164550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36166892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36167050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36169392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36169550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36301970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36302050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36304470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36304550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36306970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36307050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36309470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36309550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36311970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36312050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36314470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36314550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36316970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36317050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36319470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36319550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36452048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36452050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36454548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36454550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36457048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36457050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36459548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36459550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36462048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36462050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36464548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36464550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36467048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36467050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36469548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 36469550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36602126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36602126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36604626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36604626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36607126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36607126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36609626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36609626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36612126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36612126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36614626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36614626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36617126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36617126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36619626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36619626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36752204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36752204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36754704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36754704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36757204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36757204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36759704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36759704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36762204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36762204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36764704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36764704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36767204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36767204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36769704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36769704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36902282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36904782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36907282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36909782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36912282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36914782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36917282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 36918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36919782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37052360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37054860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37057360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37059860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37062360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37064860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37067360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37069860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37202438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37204938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37207438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37209938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37212438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37214938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37217438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37219938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37352516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37355016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37357516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37360016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37362516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37365016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37367516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37370016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37502594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37505094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37507594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37510094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37512594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37515094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37517594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37520094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37652672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37655172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37657672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37660172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37662672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37665172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37667672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37670172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37802750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37805250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37807750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37810250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37812750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37815250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37817750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37820250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37952828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37955328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37957828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37960328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37962828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37965328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37967828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 37968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 37970328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38102906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38105406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38107906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38110406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38112906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38115406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38117906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38120406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38252984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38255484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38257984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38260484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38262984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38265484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38267984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38270484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38403062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38405562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38408062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38410562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38413062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38415562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38418062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38420562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38553140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38553300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38555640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38555800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38558140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38558300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38560640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38560800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38563140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38563300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38565640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38565800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38568140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38568300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38570640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38570800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38703218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38703300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38705718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38705800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38708218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38708300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38710718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38710800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38713218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38713300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38715718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38715800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38718218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38718300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38720718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38720800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38850800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38850800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38853300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38853300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38855800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38855800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38858300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38858300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38860800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38860800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38863300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38863300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38865800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38865800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38868300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38868300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 38868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39301502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39304002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39306502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39309002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39311502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39314002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39316502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39319002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39451580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39454080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39456580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39459080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39461580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39464080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39466580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39469080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39601658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39604158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39606658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39609158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39611658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39614158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39616658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39619158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39751736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39754236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39756736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39759236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39761736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39764236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39766736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39769236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39901814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39904314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39906814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39909314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39911814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39914314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39916814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 39918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39919314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40051892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40052050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40054392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40054550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40056892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40057050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40059392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40059550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40061892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40062050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40064392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40064550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40066892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40067050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40069392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40069550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40201970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40202050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40204470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40204550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40206970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40207050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40209470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40209550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40211970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40212050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40214470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40214550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40216970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40217050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40219470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40219550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40352048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40352050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40354548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40354550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40357048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40357050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40359548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40359550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40362048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40362050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40364548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40364550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40367048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40367050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40369548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40369550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40502126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40502126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40504626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40504626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40507126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40507126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40509626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40509626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40512126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40512126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40514626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40514626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40517126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40517126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40519626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40519626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40652204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40652204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40654704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40654704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40657204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40657204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40659704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40659704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40662204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40662204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40664704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40664704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40667204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40667204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40669704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40669704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40802282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40804782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40807282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40809782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40812282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40814782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40817282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40819782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40952360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40954860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40957360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40959860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40962360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40964860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40967360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 40968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 40969860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41102438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41104938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41107438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41109938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41112438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41114938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41117438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41119938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41252516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41255016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41257516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41260016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41262516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41265016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41267516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41270016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41402594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41405094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41407594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41410094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41412594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41415094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41417594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41420094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41552672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41555172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41557672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41560172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41562672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41565172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41567672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41570172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41702750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41705250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41707750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41710250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41712750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41715250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41717750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41720250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41852828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41855328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41857828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41860328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41862828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41865328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41867828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 41868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41870328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42002906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42005406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42007906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42010406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42012906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42015406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42017906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42020406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42152984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42155484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42157984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42160484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42162984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42165484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42167984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42170484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42303062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42305562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42308062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42310562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42313062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42315562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42318062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42320562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42453140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42453300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42455640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42455800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42458140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42458300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42460640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42460800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42463140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42463300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42465640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42465800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42468140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42468300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42470640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42470800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42603218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42603300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42605718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42605800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42608218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42608300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42610718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42610800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42613218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42613300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42615718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42615800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42618218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42618300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42620718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42620800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42750800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42750800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42753300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42753300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42755800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42755800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42758300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42758300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42760800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42760800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42763300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42763300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42765800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42765800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42768300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 42768300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 42918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43201502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43204002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43206502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43209002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43211502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43214002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43216502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43219002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43351580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43354080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43356580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43359080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43361580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43364080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43366580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43369080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43501658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43504158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43506658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43509158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43511658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43514158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43516658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43519158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43651736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43654236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43656736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43659236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43661736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43664236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43666736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43669236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43801814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43804314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43806814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43809314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43811814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43814314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43816814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43819314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43951892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43952050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43954392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43954550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43956892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43957050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43959392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43959550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43961892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43962050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43964392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43964550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43966892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43967050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 43968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 43968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 43969392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43969550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44101970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44102050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44104470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44104550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44106970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44107050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44109470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44109550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44111970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44112050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44114470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44114550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44116970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44117050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44119470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44119550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44252048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44252050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44254548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44254550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44257048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44257050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44259548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44259550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44262048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44262050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44264548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44264550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44267048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44267050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44269548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44269550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44402126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44402126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44404626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44404626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44407126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44407126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44409626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44409626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44412126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44412126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44414626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44414626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44417126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44417126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44419626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44419626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44552204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44552204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44554704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44554704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44557204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44557204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44559704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44559704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44562204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44562204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44564704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44564704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44567204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44567204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44569704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44569704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44702282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44704782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44707282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44709782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44712282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44714782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44717282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44719782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44852360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44854860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44857360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44859860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44862360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44864860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44867360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 44868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44869860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45002438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45004938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45007438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45009938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45012438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45014938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45017438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45019938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45152516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45155016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45157516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45160016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45162516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45165016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45167516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45170016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45302594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45305094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45307594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45310094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45312594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45315094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45317594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45320094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45452672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45455172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45457672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45460172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45462672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45465172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45467672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45470172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45602750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45605250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45607750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45610250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45612750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45615250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45617750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45620250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45752828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45755328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45757828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45760328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45762828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45765328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45767828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45770328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45902906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45905406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45907906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45910406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45912906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45915406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45917906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 45918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 45918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45920406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46052984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46055484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46057984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46060484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46062984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46065484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46067984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46070484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46203062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46205562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46208062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46210562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46213062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46215562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46218062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46220562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46353140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46353300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46355640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46355800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46358140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46358300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46360640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46360800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46363140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46363300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46365640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46365800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46368140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46368300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46370640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46370800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46503218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46503300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46505718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46505800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46508218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46508300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46510718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46510800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46513218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46513300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46515718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46515800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46518218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46518300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46520718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46520800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46650800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46650800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46653300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46653300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46655800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46655800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46658300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46658300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46660800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46660800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46663300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46663300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46665800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46665800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46668300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46668300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 46968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47101502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47104002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47106502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47109002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47111502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47114002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47116502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47119002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47251580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47254080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47256580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47259080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47261580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47264080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47266580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47269080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47401658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47404158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47406658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47409158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47411658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47414158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47416658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47419158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47551736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47554236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47556736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47559236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47561736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47564236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47566736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47569236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47701814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47704314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47706814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47709314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47711814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47714314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47716814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47719314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47851892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47852050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47854392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47854550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47856892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47857050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47859392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47859550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47861892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47862050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47864392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47864550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47866892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47867050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47869392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47869550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48001424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48001970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48002050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48003924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48004470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48004550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48006424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48006970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48007050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48008924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48009470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48009550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48011424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48011970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48012050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48013924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48014470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48014550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48016424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48016970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48017050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48018924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48019470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48019550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48151424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48152048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48152050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48153924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48154548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48154550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48156424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48157048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48157050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48158924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48159548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48159550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48161424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48162048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48162050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48163924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48164548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48164550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48166424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48167048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48167050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48168924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48169548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48169550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48301424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48302126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48302126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48303924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48304626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48304626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48306424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48307126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48307126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48308924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48309626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48309626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48311424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48312126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48312126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48313924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48314626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48314626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48316424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48317126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48317126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48318924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48319626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48319626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48451424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48452204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48452204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48453924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48454704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48454704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48456424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48457204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48457204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48458924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48459704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48459704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48461424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48462204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48462204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48463924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48464704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48464704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48466424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48467204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48467204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48468924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48469704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48469704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48601424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48602282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48603924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48604782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48606424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48607282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48608924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48609782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48611424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48612282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48613924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48614782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48616424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48617282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48618924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48619782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48751424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48752360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48753924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48754860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48756424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48757360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48758924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48759860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48761424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48762360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48763924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48764860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48766424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48767360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48768924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48769860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48901424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48902438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48903924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48904938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48906424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48907438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48908924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48909938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48911424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48912438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48913924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48914938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48916424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48917438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 48918924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48919938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49051424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49052516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49053924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49055016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49056424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49057516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49058924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49060016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49061424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49062516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49063924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49065016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49066424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49067516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49068924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49070016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49201424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49202594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49203924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49205094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49206424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49207594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49208924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49210094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49211424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49212594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49213924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49215094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49216424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49217594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49218924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49220094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49351424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49352672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49353924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49355172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49356424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49357672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49358924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49360172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49361424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49362672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49363924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49365172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49366424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49367672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49368924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49370172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49501424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49502750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49503924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49505250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49506424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49507750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49508924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49510250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49511424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49512750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49513924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49515250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49516424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49517750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49518924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49520250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49651424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49652828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49653924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49655328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49656424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49657828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49658924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49660328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49661424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49662828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49663924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49665328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49666424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49667828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49668924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49670328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49801424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49802906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49803924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49805406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49806424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49807906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49808924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49810406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49811424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49812906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49813924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49815406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49816424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49817906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49818924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49820406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49951424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49952984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49953924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49955484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49956424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49957984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49958924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49960484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49961424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49962984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49963924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49965484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49966424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49967984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49968924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49970484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50101424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50103062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50103924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50105562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50106424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50108062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50108924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50110562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50111424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50113062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50113924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50115562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50116424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50118062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50118924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50120562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50251424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50253140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50253300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50253924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50255640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50255800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50256424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50258140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50258300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50258924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50260640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50260800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50261424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50263140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50263300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50263924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50265640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50265800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50266424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50268140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50268300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50268924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50270640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50270800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50401424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50403218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50403300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50403924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50405718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50405800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50406424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50408218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50408300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50408924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50410718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50410800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50411424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50413218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50413300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50413924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50415718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50415800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50416424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50418218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50418300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50418924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50420718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50420800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50550800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50550800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50551424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50553300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50553300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50553924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50555800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50555800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50556424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50558300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50558300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50558924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50560800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50560800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50561424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50563300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50563300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50563924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50565800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50565800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50566424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50568300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50568300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50568924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50701424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50703924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50706424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50708924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50711424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50713924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50716424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50718924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50851424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50853924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50856424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50858924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50861424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50863924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50866424.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 50868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 50868924.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51001502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51004002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51006502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51009002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51011502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51014002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51016502.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51019002.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51151580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51154080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51156580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51159080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51161580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51164080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51166580.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51169080.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51301658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51304158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51306658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51309158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51311658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51314158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51316658.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51319158.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51451736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51454236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51456736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51459236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51461736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51464236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51466736.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51469236.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51601814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51604314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51606814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51609314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51611814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51614314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51616814.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51619314.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51750878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51750878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51751892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51752050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51753378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51753378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51754392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51754550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51755878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51755878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51756892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51757050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51758378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51758378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51759392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51759550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51760878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51760878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51761892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51762050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51763378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51763378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51764392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51764550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51765878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51765878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51766892.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51767050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51768378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51768378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51769392.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51769550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51900878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51900878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51901970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51902050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51903378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51903378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51904470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51904550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51905878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51905878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51906970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51907050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51908378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51908378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51909470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51909550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51910878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51910878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51911970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51912050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51913378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51913378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51914470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51914550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51915878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51915878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51916970.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51917050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51918378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 51918378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 51919470.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51919550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52050878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52050878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52052048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52052050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52053378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52053378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52054548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52054550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52055878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52055878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52057048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52057050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52058378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52058378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52059548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52059550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52060878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52060878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52062048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52062050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52063378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52063378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52064548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52064550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52065878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52065878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52067048.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52067050.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52068378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52068378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52069548.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52069550.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52200878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52200878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52202126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52202126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52203378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52203378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52204626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52204626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52205878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52205878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52207126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52207126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52208378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52208378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52209626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52209626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52210878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52210878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52212126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52212126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52213378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52213378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52214626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52214626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52215878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52215878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52217126.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52217126.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52218378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52218378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52219626.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52219626.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52350878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52350878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52352204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52352204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52353378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52353378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52354704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52354704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52355878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52355878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52357204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52357204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52358378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52358378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52359704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52359704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52360878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52360878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52362204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52362204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52363378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52363378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52364704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52364704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52365878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52365878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52367204.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52367204.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52368378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52368378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52369704.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52369704.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52500878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52500878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52502282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52503378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52503378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52504782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52505878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52505878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52507282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52508378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52508378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52509782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52510878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52510878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52512282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52513378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52513378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52514782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52515878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52515878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52517282.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52518378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52518378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52519782.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52650878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52650878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52652360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52653378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52653378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52654860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52655878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52655878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52657360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52658378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52658378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52659860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52660878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52660878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52662360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52663378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52663378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52664860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52665878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52665878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52667360.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52668378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52668378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52669860.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52800878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52800878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52802438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52803378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52803378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52804938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52805878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52805878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52807438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52808378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52808378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52809938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52810878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52810878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52812438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52813378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52813378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52814938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52815878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52815878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52817438.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52818378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52818378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52819938.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52950878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52950878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52952516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52953378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52953378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52955016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52955878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52955878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52957516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52958378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52958378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52960016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52960878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52960878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52962516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52963378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52963378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52965016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52965878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52965878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52967516.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52968378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 52968378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 52970016.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53100878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53100878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53102594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53103378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53103378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53105094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53105878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53105878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53107594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53108378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53108378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53110094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53110878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53110878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53112594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53113378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53113378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53115094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53115878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53115878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53117594.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53118378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53118378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53120094.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53250878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53250878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53252672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53253378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53253378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53255172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53255878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53255878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53257672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53258378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53258378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53260172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53260878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53260878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53262672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53263378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53263378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53265172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53265878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53265878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53267672.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53268378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53268378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53270172.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53400878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53400878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53402750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53403378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53403378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53405250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53405878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53405878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53407750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53408378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53408378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53410250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53410878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53410878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53412750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53413378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53413378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53415250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53415878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53415878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53417750.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53418378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53418378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53420250.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53550878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53550878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53552828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53553378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53553378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53555328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53555878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53555878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53557828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53558378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53558378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53560328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53560878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53560878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53562828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53563378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53563378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53565328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53565878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53565878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53567828.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53568378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53568378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53570328.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53700878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53700878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53702906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53703378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53703378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53705406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53705878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53705878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53707906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53708378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53708378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53710406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53710878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53710878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53712906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53713378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53713378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53715406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53715878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53715878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53717906.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53718378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53718378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53720406.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53850878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53850878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53852984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53853378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53853378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53855484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53855878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53855878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53857984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53858378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53858378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53860484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53860878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53860878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53862984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53863378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53863378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53865484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53865878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53865878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53867984.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53868378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 53868378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 53870484.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54000878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54000878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54003062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54003378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54003378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54005562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54005878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54005878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54008062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54008378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54008378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54010562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54010878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54010878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54013062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54013378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54013378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54015562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54015878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54015878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54018062.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54018378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54018378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54020562.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54150878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54150878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54153140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54153300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54153378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54153378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54155640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54155800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54155878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54155878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54158140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54158300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54158378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54158378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54160640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54160800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54160878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54160878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54163140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54163300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54163378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54163378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54165640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54165800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54165878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54165878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54168140.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54168300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54168378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54168378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54170640.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54170800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54300878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54300878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54303218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54303300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54303378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54303378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54305718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54305800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54305878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54305878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54308218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54308300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54308378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54308378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54310718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54310800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54310878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54310878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54313218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54313300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54313378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54313378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54315718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54315800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54315878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54315878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54318218.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54318300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54318378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54318378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54320718.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54320800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54450800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54450800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54450878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54450878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54453300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54453300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54453378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54453378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54455800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54455800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54455878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54455878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54458300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54458300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54458378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54458378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54460800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54460800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54460878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54460878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54463300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54463300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54463378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54463378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54465800.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54465800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54465878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54465878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54468300.0 ps Write Leveling @ DQS ck = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54468300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54468378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54468378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54600878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54600878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54603378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54603378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54605878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54605878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54608378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54608378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54610878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54610878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54613378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54613378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54615878.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54615878.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54618378.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 54618378.0 ps Write Leveling @ DQS ck = 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54740800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 DLL Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Output Drive Strength = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 ODT Rtt = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Additive Latency = 0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Write Levelization = Disabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 TDQS Enable = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54745800.0 ps INFO: Load Mode 1 Qoff = Enabled -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54795800.0 ps INFO: Precharge All -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 54825800.0 ps INFO: Refresh -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55213300.0 ps INFO: Activate bank 0 row 0000 - prev_cmd=Read , prev_time=23168300 ps, difference=32045000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55230800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Activate , prev_time=55213300 ps, difference=17500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55230800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55240800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55230800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55244550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55245800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55247050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55248300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55249550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55250800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55252050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55253300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55254550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 3d -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55255800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 2c -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55257050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = f1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55258300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 75 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55259550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55260800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55262050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = d2 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55263300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = cf -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55278300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55240800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55280800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55292050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = c1 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55293300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 51 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55294550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = ad -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55295800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = d0 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55297050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 8c -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55298300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 29 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55299550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55300800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 91 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55470800.0 ps INFO: Write bank 0 col 000, auto precharge 0 - prev_cmd=Read , prev_time=55278300 ps, difference=192500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55470800.0 ps INFO: Sync On Die Termination Rtt_NOM = 40 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55480800.0 ps INFO: Write bank 0 col 008, auto precharge 0 - prev_cmd=Write , prev_time=55470800 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55484550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55485800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55487050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55488300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55489550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55490800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55492050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55493300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55494550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000008 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55495800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 00000009 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55497050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000a data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55498300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000b data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55499550.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000c data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55500800.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000d data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55502050.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000e data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps ERROR: DQS bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps ERROR: DQS_N bit 0 latching edge required during the preceding clock period. -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55503300.0 ps INFO: WRITE @ DQS= bank = 0 row = 0000 col = 0000000f data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55518300.0 ps INFO: Read bank 0 col 000, auto precharge 0 - prev_cmd=Write , prev_time=55480800 ps, difference=37500 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55520800.0 ps INFO: Sync On Die Termination Rtt_NOM = 0 Ohm -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 55528300.0 ps INFO: Read bank 0 col 008, auto precharge 0 - prev_cmd=Read , prev_time=55518300 ps, difference=10000 ps -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55532050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55533300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55534550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55535800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55537050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55538300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55539550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55540800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55542050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000008 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55543300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000009 data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55544550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000a data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55545800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000b data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55547050.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000c data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55548300.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000d data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55549550.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000e data = 77 -ddr3_dimm_micron_sim.ddr3_dimm.U1.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 00 -ddr3_dimm_micron_sim.ddr3_dimm.U2.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 11 -ddr3_dimm_micron_sim.ddr3_dimm.U3.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 22 -ddr3_dimm_micron_sim.ddr3_dimm.U4.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 33 -ddr3_dimm_micron_sim.ddr3_dimm.U6.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 44 -ddr3_dimm_micron_sim.ddr3_dimm.U7.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 55 -ddr3_dimm_micron_sim.ddr3_dimm.U8.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 66 -ddr3_dimm_micron_sim.ddr3_dimm.U9.data_task: at time 55550800.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 0000000f data = 77 -$stop called at time : 55575 ns : File "/home/angelo/Desktop/switch_fpga/switch_fpga.srcs/sim_1/new/ddr3_dimm_micron_sim.v" Line 208 -run: Time (s): cpu = 00:05:23 ; elapsed = 00:09:28 . Memory (MB): peak = 10222.301 ; gain = 5.004 ; free physical = 573 ; free virtual = 22626 -save_wave_config {/home/angelo/Desktop/switch_fpga/ddr3_dimm_micron_sim_behav.wcfg} diff --git a/new_formal.gtkw b/new_formal.gtkw deleted file mode 100644 index c974707..0000000 --- a/new_formal.gtkw +++ /dev/null @@ -1,90 +0,0 @@ -[*] -[*] GTKWave Analyzer v3.4.0 (w)1999-2022 BSI -[*] Tue Jun 27 09:57:53 2023 -[*] -[dumpfile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/ddr3_controller/engine_0/trace0.vcd" -[dumpfile_mtime] "Tue Jun 27 08:16:33 2023" -[dumpfile_size] 370354 -[savefile] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/new_formal.gtkw" -[timestart] 167 -[size] 1848 1126 -[pos] -51 -51 -*-4.943873 244 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -[sst_width] 369 -[signals_width] 430 -[sst_expanded] 1 -[sst_vpaned_height] 743 -@420 -smt_step -@28 -ddr3_controller.i_controller_clk -ddr3_controller.i_rst_n -@24 -ddr3_controller.state_calibrate[3:0] -ddr3_controller.instruction_address[4:0] -@28 -ddr3_controller.reset_done -@200 -- --WB Interface -@28 -ddr3_controller.i_wb_cyc -ddr3_controller.o_wb_stall -ddr3_controller.i_wb_stb -ddr3_controller.i_wb_we -@22 -ddr3_controller.i_wb_addr[23:0] -ddr3_controller.i_wb_data[511:0] -ddr3_controller.i_wb_sel[63:0] -@28 -ddr3_controller.o_wb_ack -@200 -- --Internals -@28 -ddr3_controller.stage1_pending -ddr3_controller.stage1_we -@24 -ddr3_controller.stage1_bank[2:0] -ddr3_controller.stage1_col[9:0] -@25 -ddr3_controller.stage1_row[13:0] -@24 -ddr3_controller.stage1_stall -@204 -- -@24 -ddr3_controller.stage2_pending -ddr3_controller.stage2_we -ddr3_controller.stage2_bank[2:0] -ddr3_controller.stage2_col[9:0] -ddr3_controller.stage2_row[13:0] -ddr3_controller.stage2_stall -@200 -- -@28 -ddr3_controller.bank_status_q[7:0] -@22 -ddr3_controller.delay_before_precharge_counter_q<1>[3:0] -ddr3_controller.delay_before_precharge_counter_q<2>[3:0] -ddr3_controller.delay_before_activate_counter_q<1>[3:0] -ddr3_controller.delay_before_activate_counter_q<2>[3:0] -ddr3_controller.delay_before_read_counter_q<1>[3:0] -ddr3_controller.delay_before_read_counter_q<2>[3:0] -ddr3_controller.delay_before_write_counter_q<1>[3:0] -ddr3_controller.delay_before_write_counter_q<2>[3:0] -@200 -- --CMD -@28 -+{ddr3_controller.[ACT] cmd_d<0>[23:0]} ddr3_controller.cmd_d<0>[23:0] -+{ddr3_controller.[PRE] cmd_d<1>[23:0]} ddr3_controller.cmd_d<1>[23:0] -+{ddr3_controller.[RD] cmd_d<2>[23:0]} ddr3_controller.cmd_d<2>[23:0] -+{ddr3_controller.[WR] cmd_d<3>[23:0]} ddr3_controller.cmd_d<3>[23:0] -@200 -- --Formal -@24 -ddr3_controller.f_index[4:0] -[pattern_trace] 1 -[pattern_trace] 0 diff --git a/temp.log b/temp.log deleted file mode 100644 index 16efc0b..0000000 --- a/temp.log +++ /dev/null @@ -1,12054 +0,0 @@ -relaunch_sim -INFO: xsimkernel Simulation Memory Usage: 240132 KB (Peak: 297928 KB), Simulation CPU Usage: 46220 ms -Command: launch_simulation -step compile -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-2] XSim::Compile design -INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xvlog --incr --relax -L uvm -prj ddr3_dimm_micron_sim_vlog.prj -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_controller -WARNING: [VRFC 10-3380] identifier 'PRECHARGE_TO_ACTIVATE_DELAY' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:189] -INFO: [VRFC 10-311] analyzing module mini_fifo -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_phy -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:321] -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:364] -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_top -Waiting for jobs to finish... -No pending jobs, compilation finished. -INFO: [USF-XSim-69] 'compile' step finished in '3' seconds -launch_simulation: Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 8211.539 ; gain = 0.000 ; free physical = 1165 ; free virtual = 23750 -Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-3] XSim::Elaborate design -INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Using 8 slave threads. -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:201] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:132] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:153] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:154] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:155] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:162] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:247] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:272] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:273] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:278] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:280] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:316] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:322] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:323] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:371] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:372] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:423] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:424] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:449] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:450] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:455] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:457] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:494] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:495] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:496] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:503] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:533] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:572] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:573] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:577] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:579] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:628] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:629] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:697] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:698] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:744] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim_behav -run_program: Time (s): cpu = 00:02:59 ; elapsed = 00:02:22 . Memory (MB): peak = 8211.539 ; gain = 0.000 ; free physical = 1264 ; free virtual = 23313 -INFO: [USF-XSim-69] 'elaborate' step finished in '142' seconds -launch_simulation: Time (s): cpu = 00:02:59 ; elapsed = 00:02:22 . Memory (MB): peak = 8211.539 ; gain = 0.000 ; free physical = 1264 ; free virtual = 23313 -Time resolution is 1 ps -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> run: Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 8216.422 ; gain = 0.000 ; free physical = 1081 ; free virtual = 23143 -relaunch_xsim_kernel: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 8216.422 ; gain = 4.883 ; free physical = 1081 ; free virtual = 23143 -relaunch_sim: Time (s): cpu = 00:03:53 ; elapsed = 00:02:43 . Memory (MB): peak = 8216.422 ; gain = 4.883 ; free physical = 1081 ; free virtual = 23143 -run all -[370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[237500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43461402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43463902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43466402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43468902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43471402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43476402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43611480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43613980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43616480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43618980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43621480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43626480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45712600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45715100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45717600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45720100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45722600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45725100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45727600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45730100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46311402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46313902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46316402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46318902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46321402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46323902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46326402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46328902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46461480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46463980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46466480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46468980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46471480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46473980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46476480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46478980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49161402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49163902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49166402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49168902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49171402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49173902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49176402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49178902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49311480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49313980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49316480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49318980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49321480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49323980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49326480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49328980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52011402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52013902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52016402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52018902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52021402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52023902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52026402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52028902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52161480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52163980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52166480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52168980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52171480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52173980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52176480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52178980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54861402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54863902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54866402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54868902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54871402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54873902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54876402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54878902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55011480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55013980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55016480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55018980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55021480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55023980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55026480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55028980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57711402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57713902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57716402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57718902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57721402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57723902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57726402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57728902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57861480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57863980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57866480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57868980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57871480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57873980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57876480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57878980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60561402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60563902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60566402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60568902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60571402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60573902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60576402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60578902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60711480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60713980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60716480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60718980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60721480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60723980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60726480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60728980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63411402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63413902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63416402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63418902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63421402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63423902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63426402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63428902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63561480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63563980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63566480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63568980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63571480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63573980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63576480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63578980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65512600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65515100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65517600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65520100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65522600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65525100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65527600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65530100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[22660000 ps] MRS -> -[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 0) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [20000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [20000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 66620000 ps -Time Done: 90970000 ps - -[10000 ps] RD @ (0, 992) -> -[ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 91050000.0 ps -[167500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [37500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [20000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [20000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 91070000 ps -Time Done: 115900000 ps - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 115980000.0 ps -[107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [20000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> -[10000 ps] WR @ (0, 72) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 16383) -> -[17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [20000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> -[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> -[10000 ps] WR @ (6, 160) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (6, 16383) -> -[17500 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [20000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> -[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[20000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> -[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> -[10000 ps] RD @ (3, 184) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (3, 16383) -> -[15000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [20000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 116000000 ps -Time Done: 140960000 ps -Diff: 24_960 ns - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 141040000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> -[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> -[15000 ps] NOP -> [30000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [125000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 12761) -> [17500 ps] WR @ (0, 952) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [12500 ps] ACT @ (4, 10602) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5206) -> [10000 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [17500 ps] WR @ (0, 944) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 890) -> -[17500 ps] WR @ (0, 944) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16194) -> [17500 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [17500 ps] WR @ (0, 928) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6482) -> -[17500 ps] WR @ (0, 928) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5402) -> [17500 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[17500 ps] WR @ (0, 920) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [17500 ps] WR @ (4, 920) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8836) -> [17500 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[17500 ps] WR @ (0, 912) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [17500 ps] WR @ (4, 912) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14428) -> [17500 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[17500 ps] WR @ (0, 896) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [17500 ps] WR @ (4, 896) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3636) -> [17500 ps] WR @ (0, 896) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> -[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [17500 ps] WR @ (0, 888) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7069) -> -[17500 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> -[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [17500 ps] WR @ (0, 872) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12661) -> -[17500 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> -[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [17500 ps] WR @ (0, 864) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1869) -> -[17500 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> -[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> -[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> -[17500 ps] WR @ (4, 848) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5303) -> [17500 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> -[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> -[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> -[17500 ps] WR @ (4, 840) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10895) -> [17500 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> -[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> -[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> -[17500 ps] WR @ (4, 832) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 103) -> [17500 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> -[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> -[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[17500 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5695) -> [17500 ps] WR @ (0, 816) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3536) -> [17500 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[17500 ps] WR @ (4, 816) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [125000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 7500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [17500 ps] WR @ (0, 808) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10208) -> -[17500 ps] WR @ (0, 808) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9128) -> [17500 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [17500 ps] WR @ (0, 800) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15800) -> -[17500 ps] WR @ (0, 792) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14720) -> [17500 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> -[17500 ps] WR @ (0, 784) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [17500 ps] WR @ (4, 784) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1770) -> [17500 ps] WR @ (0, 784) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> -[17500 ps] WR @ (0, 776) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [17500 ps] WR @ (4, 776) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7362) -> [17500 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> -[17500 ps] WR @ (0, 760) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [17500 ps] WR @ (4, 760) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12954) -> [17500 ps] WR @ (0, 760) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> -[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [17500 ps] WR @ (0, 752) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3) -> -[17500 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> -[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [17500 ps] WR @ (0, 736) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5595) -> -[17500 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> -[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [17500 ps] WR @ (0, 728) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11187) -> -[17500 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> -[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> -[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> -[17500 ps] WR @ (4, 720) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14621) -> [17500 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> -[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> -[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> -[17500 ps] WR @ (4, 704) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3829) -> [17500 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> -[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> -[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> -[17500 ps] WR @ (4, 696) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9421) -> [17500 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> -[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> -[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> -[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> -[17500 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15013) -> [17500 ps] WR @ (0, 680) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12854) -> [17500 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> -[17500 ps] WR @ (4, 680) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> -[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> -[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> -[17500 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] NOP -> [15000 ps] WR @ (0, 672) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3142) -> -[17500 ps] WR @ (0, 672) -> [95000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2062) -> -[17500 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [22500 ps] ACT @ (0, 15209) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> -[17500 ps] WR @ (4, 664) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [17500 ps] WR @ (0, 664) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7654) -> [17500 ps] WR @ (4, 656) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> -[10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [17500 ps] WR @ (4, 648) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11088) -> -[17500 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> -[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [17500 ps] WR @ (4, 640) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 296) -> -[17500 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> -[10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [17500 ps] WR @ (4, 624) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5888) -> -[17500 ps] WR @ (0, 624) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> -[10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> -[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> -[17500 ps] WR @ (0, 616) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9321) -> [17500 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> -[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> -[17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> -[17500 ps] WR @ (0, 608) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14913) -> [17500 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> -[10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> -[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> -[17500 ps] WR @ (0, 592) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4121) -> [17500 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> -[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> -[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> -[10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> -[17500 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9713) -> [17500 ps] WR @ (4, 584) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7555) -> [17500 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> -[17500 ps] WR @ (0, 576) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> -[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> -[10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> -[17500 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15305) -> [17500 ps] WR @ (4, 568) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13147) -> [17500 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> -[17500 ps] WR @ (0, 568) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> -[17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> -[10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> -[17500 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4513) -> [17500 ps] WR @ (4, 560) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2355) -> [17500 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> -[17500 ps] WR @ (0, 560) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> -[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> -[10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [17500 ps] WR @ (0, 544) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6868) -> -[17500 ps] WR @ (0, 544) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5788) -> [17500 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [17500 ps] WR @ (0, 536) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12460) -> -[17500 ps] WR @ (0, 536) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11380) -> [17500 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [145000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [12500 ps] ACT @ (0, 2747) -> [17500 ps] WR @ (0, 528) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 588) -> [17500 ps] WR @ (4, 528) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> -[10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [17500 ps] WR @ (4, 512) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4022) -> -[17500 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> -[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [17500 ps] WR @ (4, 504) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9614) -> -[17500 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> -[10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [17500 ps] WR @ (4, 496) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15206) -> -[17500 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> -[10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> -[17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> -[17500 ps] WR @ (0, 480) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2255) -> [17500 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> -[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> -[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> -[17500 ps] WR @ (0, 472) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7847) -> [17500 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> -[10000 ps] WR @ (0, 464) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2451) -> [10000 ps] ACT @ (0, 3531) -> -[17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> -[17500 ps] WR @ (0, 456) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13439) -> [17500 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> -[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> -[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> -[10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> -[17500 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2647) -> [17500 ps] WR @ (4, 448) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 489) -> [17500 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> -[17500 ps] WR @ (0, 440) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> -[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> -[10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> -[17500 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8239) -> [17500 ps] WR @ (4, 440) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6081) -> [17500 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> -[17500 ps] WR @ (0, 432) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> -[17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> -[10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> -[17500 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13831) -> [17500 ps] WR @ (4, 424) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11673) -> [17500 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> -[17500 ps] WR @ (0, 424) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> -[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> -[10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [17500 ps] WR @ (0, 416) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16186) -> -[17500 ps] WR @ (0, 408) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15106) -> [17500 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [17500 ps] WR @ (0, 400) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5394) -> -[17500 ps] WR @ (0, 400) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4314) -> [17500 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [17500 ps] WR @ (0, 392) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10986) -> -[17500 ps] WR @ (0, 392) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9906) -> [17500 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [75000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (4, 7748) -> [10000 ps] ACT @ (0, 6669) -> [ 7500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> -[10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [17500 ps] WR @ (4, 376) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13340) -> -[17500 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> -[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [17500 ps] WR @ (4, 368) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2548) -> -[17500 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> -[10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [17500 ps] WR @ (4, 360) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8140) -> -[17500 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> -[10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> -[17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[17500 ps] WR @ (0, 344) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11573) -> [17500 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> -[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> -[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[17500 ps] WR @ (0, 336) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 781) -> [17500 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> -[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> -[17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[17500 ps] WR @ (0, 328) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6373) -> [17500 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> -[10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> -[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> -[10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> -[17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [17500 ps] WR @ (4, 312) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9807) -> [17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> -[17500 ps] WR @ (0, 312) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> -[17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> -[10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> -[17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15399) -> [17500 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> -[17500 ps] WR @ (0, 296) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> -[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> -[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> -[17500 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [15000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [17500 ps] WR @ (4, 288) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4607) -> [17500 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> -[17500 ps] WR @ (0, 288) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> -[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [17500 ps] WR @ (0, 280) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9120) -> -[17500 ps] WR @ (0, 280) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8040) -> [17500 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [17500 ps] WR @ (0, 264) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14712) -> -[17500 ps] WR @ (0, 264) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13632) -> [17500 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> -[15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [17500 ps] WR @ (0, 256) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3920) -> -[17500 ps] WR @ (0, 256) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2840) -> [17500 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> -[15000 ps] NOP -> [30000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 8432) -> [17500 ps] WR @ (4, 248) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> -[12500 ps] ACT @ (0, 6274) -> [17500 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> -[10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> -[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> -[17500 ps] WR @ (4, 232) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11866) -> [17500 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> -[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> -[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> -[17500 ps] WR @ (4, 224) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1074) -> [17500 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> -[10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> -[17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> -[10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> -[17500 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6666) -> [17500 ps] WR @ (0, 208) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4507) -> [17500 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> -[17500 ps] WR @ (4, 208) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> -[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> -[10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> -[17500 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12258) -> [17500 ps] WR @ (0, 200) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10099) -> [17500 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> -[17500 ps] WR @ (4, 200) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> -[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> -[10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> -[17500 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1466) -> [17500 ps] WR @ (0, 192) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15691) -> [17500 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> -[17500 ps] WR @ (4, 184) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> -[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> -[10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [17500 ps] WR @ (4, 176) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3820) -> -[17500 ps] WR @ (4, 176) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2741) -> [17500 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [17500 ps] WR @ (4, 168) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9412) -> -[17500 ps] WR @ (4, 168) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8333) -> [17500 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [17500 ps] WR @ (4, 152) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15004) -> -[17500 ps] WR @ (4, 152) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13925) -> [17500 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> -[17500 ps] WR @ (4, 144) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [17500 ps] WR @ (0, 144) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 974) -> [17500 ps] WR @ (4, 144) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> -[17500 ps] WR @ (4, 136) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [17500 ps] WR @ (0, 136) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6566) -> [17500 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> -[17500 ps] WR @ (4, 120) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [17500 ps] WR @ (0, 120) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12158) -> [17500 ps] WR @ (4, 120) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> -[10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [17500 ps] WR @ (4, 112) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15592) -> -[17500 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [25000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> -[125000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> -[ 7500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> -[17500 ps] WR @ (4, 96) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4800) -> [17500 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> -[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> -[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> -[17500 ps] WR @ (4, 88) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10392) -> [17500 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> -[25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> -[10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> -[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> -[10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> -[17500 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15984) -> [17500 ps] WR @ (0, 72) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13825) -> [17500 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> -[17500 ps] WR @ (4, 72) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> -[17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> -[10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> -[17500 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5192) -> [17500 ps] WR @ (0, 64) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3033) -> [17500 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> -[17500 ps] WR @ (4, 64) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> -[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> -[10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> -[17500 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [15000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10784) -> [17500 ps] WR @ (0, 56) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8625) -> [17500 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> -[17500 ps] WR @ (4, 48) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> -[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> -[10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [17500 ps] WR @ (4, 40) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13138) -> -[17500 ps] WR @ (4, 40) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12059) -> [17500 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [17500 ps] WR @ (4, 32) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2346) -> -[17500 ps] WR @ (4, 32) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1267) -> [17500 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> -[15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [17500 ps] WR @ (4, 24) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7938) -> -[17500 ps] WR @ (4, 16) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6859) -> [17500 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [25000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> -[17500 ps] WR @ (4, 8) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [17500 ps] WR @ (0, 8) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10292) -> [17500 ps] WR @ (4, 8) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> -[17500 ps] WR @ (4, 0) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [17500 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [22500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [15000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [17500 ps] WR @ (3, 1016) -> -[15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10488) -> [17500 ps] WR @ (7, 1016) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8331) -> -[12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> -[17500 ps] WR @ (7, 1016) -> [12500 ps] ACT @ (4, 7251) -> [12500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7251) -> [12500 ps] PRE @ (4) -> -[ 5000 ps] WR @ (3, 1008) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> [15000 ps] PRE @ (0) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 4014) -> [10000 ps] ACT @ (7, 5092) -> [17500 ps] WR @ (7, 1008) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1855) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> -[15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16081) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13922) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13922) -> -[17500 ps] WR @ (3, 1000) -> [15000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11764) -> [12500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12843) -> -[17500 ps] WR @ (3, 1000) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [12500 ps] ACT @ (0, 10685) -> -[12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10684) -> [12500 ps] PRE @ (0) -> [ 5000 ps] WR @ (7, 1000) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [15000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 7447) -> -[10000 ps] ACT @ (3, 8526) -> [17500 ps] WR @ (3, 1000) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> -[15000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5288) -> [17500 ps] WR @ (7, 992) -> [15000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3130) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] NOP -> -[ 7500 ps] ACT @ (3, 3130) -> [17500 ps] WR @ (3, 992) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 2051) -> [10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> -[17500 ps] WR @ (3, 992) -> [12500 ps] ACT @ (0, 16277) -> [10000 ps] ACT @ (7, 16276) -> [17500 ps] WR @ (7, 984) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [15000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 13039) -> -[10000 ps] ACT @ (3, 14118) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> -[15000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> -[17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10880) -> [17500 ps] WR @ (7, 984) -> [15000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[17500 ps] WR @ (7, 976) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [15000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3326) -> [17500 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> -[25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> -[17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> -[10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> -[17500 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [15000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [17500 ps] WR @ (3, 968) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6759) -> [17500 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> -[17500 ps] WR @ (7, 960) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> -[17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> -[10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> -[17500 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [15000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [17500 ps] WR @ (3, 952) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12351) -> [17500 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> -[17500 ps] WR @ (7, 952) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> -[17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> -[10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> -[17500 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [15000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [17500 ps] WR @ (3, 944) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1559) -> [17500 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> -[17500 ps] WR @ (7, 944) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> -[10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [17500 ps] WR @ (7, 928) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6072) -> -[17500 ps] WR @ (7, 928) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4993) -> [17500 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [17500 ps] WR @ (7, 920) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11664) -> -[17500 ps] WR @ (7, 920) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10585) -> [17500 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> -[15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [17500 ps] WR @ (7, 912) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 872) -> -[17500 ps] WR @ (7, 912) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16177) -> [17500 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[17500 ps] WR @ (7, 896) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [17500 ps] WR @ (3, 896) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3226) -> [17500 ps] WR @ (7, 896) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[17500 ps] WR @ (7, 888) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [17500 ps] WR @ (3, 888) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8818) -> [17500 ps] WR @ (7, 888) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[17500 ps] WR @ (7, 880) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [17500 ps] WR @ (3, 880) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14410) -> [17500 ps] WR @ (7, 872) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> -[10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [17500 ps] WR @ (7, 864) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1460) -> -[17500 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [25000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> -[10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [17500 ps] WR @ (7, 856) -> -[15000 ps] NOP -> [30000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [125000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 7052) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [22500 ps] ACT @ (7, 3814) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> -[17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1656) -> -[10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> -[17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [15000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [17500 ps] WR @ (7, 840) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> -[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12644) -> [17500 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> -[17500 ps] WR @ (3, 840) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> -[17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> -[10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> -[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [17500 ps] WR @ (3, 832) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 773) -> -[17500 ps] WR @ (3, 832) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16077) -> [17500 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> -[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [17500 ps] WR @ (3, 816) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6365) -> -[17500 ps] WR @ (3, 816) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5285) -> [17500 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> -[15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [17500 ps] WR @ (3, 808) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11957) -> -[17500 ps] WR @ (3, 808) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10877) -> [17500 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> [25000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[17500 ps] WR @ (3, 800) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [17500 ps] WR @ (7, 800) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14311) -> [17500 ps] WR @ (3, 792) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[17500 ps] WR @ (3, 784) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [17500 ps] WR @ (7, 784) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3519) -> [17500 ps] WR @ (3, 784) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[17500 ps] WR @ (3, 776) -> [15000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [17500 ps] WR @ (7, 776) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [15000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9111) -> [17500 ps] WR @ (3, 776) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [25000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [10000 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (4, 2852) -> -[10000 ps] ACT @ (0, 1773) -> [25000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 694) -> [10000 ps] ACT @ (4, 15998) -> [ 5000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [15000 ps] RD @ (0, 952) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11682) -> -[15000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10602) -> [15000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8444) -> -[10000 ps] ACT @ (0, 7365) -> [ 5000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [15000 ps] RD @ (0, 944) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 890) -> -[15000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16194) -> [15000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14036) -> -[10000 ps] ACT @ (0, 12957) -> [ 5000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [15000 ps] RD @ (0, 928) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6482) -> -[15000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5402) -> [15000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3244) -> -[10000 ps] ACT @ (0, 2165) -> [ 5000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15311) -> [10000 ps] ACT @ (0, 14232) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[15000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [15000 ps] RD @ (4, 920) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9915) -> [15000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8836) -> [15000 ps] RD @ (0, 920) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6678) -> [10000 ps] ACT @ (4, 5598) -> [ 5000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[15000 ps] RD @ (0, 912) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [15000 ps] RD @ (4, 912) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15507) -> [15000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14428) -> [15000 ps] RD @ (0, 904) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12270) -> [10000 ps] ACT @ (4, 11190) -> [ 5000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[15000 ps] RD @ (0, 896) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [15000 ps] RD @ (4, 896) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4715) -> [15000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3636) -> [15000 ps] RD @ (0, 896) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1478) -> [10000 ps] ACT @ (4, 398) -> [ 5000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13545) -> [10000 ps] ACT @ (4, 12465) -> [ 5000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (4, 888) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [27500 ps] PRE @ (4) -> -[10000 ps] NOP -> [ 7500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (0, 9228) -> [15000 ps] RD @ (0, 888) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8149) -> -[15000 ps] RD @ (0, 880) -> [15000 ps] ACT @ (4, 7069) -> [15000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> -[15000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4911) -> [10000 ps] ACT @ (0, 3832) -> -[ 5000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> -[10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> -[15000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14820) -> [15000 ps] RD @ (0, 872) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13741) -> [15000 ps] RD @ (0, 872) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12661) -> [15000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> -[15000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10503) -> [10000 ps] ACT @ (0, 9424) -> -[ 5000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> -[10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> -[15000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4028) -> [15000 ps] RD @ (0, 864) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2949) -> [15000 ps] RD @ (0, 864) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1869) -> [15000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> -[15000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16095) -> [10000 ps] ACT @ (0, 15016) -> -[ 5000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> -[10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11778) -> [10000 ps] ACT @ (0, 10699) -> [ 5000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [15000 ps] RD @ (4, 848) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6382) -> -[15000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5303) -> [15000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3145) -> -[10000 ps] ACT @ (4, 2065) -> [ 5000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [15000 ps] RD @ (4, 840) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11974) -> -[15000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10895) -> [15000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8737) -> -[10000 ps] ACT @ (4, 7657) -> [ 5000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [15000 ps] RD @ (4, 832) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1182) -> -[15000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 103) -> [15000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14329) -> -[10000 ps] ACT @ (4, 13249) -> [ 5000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10012) -> [10000 ps] ACT @ (4, 8932) -> [ 5000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[15000 ps] RD @ (4, 816) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [15000 ps] RD @ (0, 816) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4616) -> [15000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3536) -> [15000 ps] RD @ (4, 816) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1378) -> [10000 ps] ACT @ (0, 299) -> [ 5000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[15000 ps] RD @ (4, 808) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [15000 ps] RD @ (0, 808) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10208) -> [15000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9128) -> [15000 ps] RD @ (4, 808) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6970) -> [10000 ps] ACT @ (0, 5891) -> [ 5000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[15000 ps] RD @ (4, 800) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [15000 ps] RD @ (0, 800) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15800) -> [15000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14720) -> [15000 ps] RD @ (4, 792) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12562) -> [10000 ps] ACT @ (0, 11483) -> [ 5000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8245) -> [10000 ps] ACT @ (0, 7166) -> [ 5000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [15000 ps] RD @ (4, 784) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2849) -> [15000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1770) -> -[15000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15996) -> [10000 ps] ACT @ (4, 14916) -> [ 5000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> -[10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [15000 ps] RD @ (4, 776) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8441) -> [15000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7362) -> -[15000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5204) -> [10000 ps] ACT @ (4, 4124) -> [ 5000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [15000 ps] RD @ (4, 760) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14033) -> [15000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12954) -> -[15000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10796) -> [10000 ps] ACT @ (4, 9716) -> [ 5000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> -[10000 ps] RD @ (0, 752) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6479) -> [10000 ps] ACT @ (4, 5399) -> -[ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> -[15000 ps] RD @ (0, 752) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1083) -> [15000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3) -> [15000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14229) -> [10000 ps] ACT @ (0, 13150) -> [ 5000 ps] RD @ (4, 744) -> -[10000 ps] RD @ (0, 744) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> -[ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> -[15000 ps] RD @ (0, 736) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6675) -> [15000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5595) -> [15000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3437) -> [10000 ps] ACT @ (0, 2358) -> [ 5000 ps] RD @ (4, 736) -> -[10000 ps] RD @ (0, 736) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> -[ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> -[15000 ps] RD @ (0, 728) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12267) -> [15000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11187) -> [15000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9029) -> [10000 ps] ACT @ (0, 7950) -> [ 5000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (0, 720) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> -[ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4712) -> -[10000 ps] ACT @ (0, 3633) -> [ 5000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> -[15000 ps] RD @ (0, 720) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 395) -> [15000 ps] RD @ (4, 720) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15700) -> [15000 ps] RD @ (4, 712) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14621) -> [15000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> -[15000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12463) -> [10000 ps] ACT @ (4, 11383) -> -[ 5000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [ 7500 ps] NOP -> [20000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10304) -> -[15000 ps] RD @ (4, 712) -> [137500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9225) -> -[15000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [25000 ps] ACT @ (4, 5987) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> -[15000 ps] RD @ (0, 704) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [15000 ps] RD @ (4, 704) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15896) -> [15000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14817) -> [15000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12659) -> [10000 ps] ACT @ (4, 11579) -> [ 5000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> -[15000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [15000 ps] RD @ (4, 688) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5104) -> [15000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4025) -> [15000 ps] RD @ (0, 688) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1866) -> -[15000 ps] RD @ (4, 688) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16092) -> [10000 ps] ACT @ (0, 15013) -> [ 5000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [15000 ps] RD @ (0, 680) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8538) -> [15000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7458) -> -[15000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5300) -> [10000 ps] ACT @ (0, 4221) -> [ 5000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [15000 ps] RD @ (0, 664) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14130) -> [15000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13050) -> -[15000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10892) -> [10000 ps] ACT @ (0, 9813) -> [ 5000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [15000 ps] RD @ (0, 656) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3338) -> [15000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2258) -> -[15000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 100) -> [15000 ps] RD @ (0, 656) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14326) -> [10000 ps] ACT @ (4, 13246) -> [ 5000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (4, 648) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> -[ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> -[15000 ps] RD @ (4, 640) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6771) -> [15000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5692) -> [15000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3534) -> [10000 ps] ACT @ (4, 2454) -> [ 5000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (4, 640) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> -[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> -[15000 ps] RD @ (4, 632) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12363) -> [15000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11284) -> [15000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9126) -> [10000 ps] ACT @ (4, 8046) -> [ 5000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 624) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> -[ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> -[15000 ps] RD @ (4, 624) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 492) -> [15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15797) -> [15000 ps] RD @ (0, 616) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14717) -> [15000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> -[15000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12559) -> [10000 ps] ACT @ (0, 11480) -> -[ 5000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> -[10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> -[15000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6084) -> [15000 ps] RD @ (0, 608) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5005) -> [15000 ps] RD @ (0, 608) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3925) -> [15000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> -[15000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1767) -> [10000 ps] ACT @ (0, 688) -> -[ 5000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> -[10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> -[15000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11676) -> [15000 ps] RD @ (0, 600) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10597) -> [15000 ps] RD @ (0, 600) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9517) -> [15000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> -[15000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7359) -> [10000 ps] ACT @ (0, 6280) -> -[ 5000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> -[10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> -[15000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 884) -> [15000 ps] RD @ (0, 592) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16189) -> [15000 ps] RD @ (0, 584) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15109) -> [15000 ps] RD @ (4, 584) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14030) -> -[15000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12951) -> [15000 ps] RD @ (0, 584) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10793) -> -[10000 ps] ACT @ (4, 9713) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [15000 ps] RD @ (4, 576) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3238) -> -[15000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2159) -> [15000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1) -> -[10000 ps] ACT @ (4, 15305) -> [ 5000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [15000 ps] RD @ (4, 568) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8830) -> -[15000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7751) -> [15000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5593) -> -[10000 ps] ACT @ (4, 4513) -> [ 5000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [15000 ps] RD @ (4, 552) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14422) -> -[15000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13343) -> [15000 ps] RD @ (0, 552) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11184) -> [15000 ps] RD @ (4, 552) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9026) -> [10000 ps] ACT @ (0, 7947) -> [ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> -[15000 ps] RD @ (4, 544) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [15000 ps] RD @ (0, 544) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1472) -> [15000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 392) -> [15000 ps] RD @ (4, 544) -> -[27500 ps] PRE @ (4) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> [167500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 14618) -> [10000 ps] ACT @ (0, 13539) -> [ 5000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 536) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> -[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> -[15000 ps] RD @ (0, 528) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7064) -> [15000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5984) -> [15000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3826) -> [10000 ps] ACT @ (0, 2747) -> [ 5000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (0, 528) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> -[15000 ps] RD @ (0, 520) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12656) -> [15000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11576) -> [15000 ps] RD @ (4, 520) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9418) -> [15000 ps] RD @ (0, 520) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> -[15000 ps] RD @ (0, 520) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7260) -> [10000 ps] ACT @ (4, 6180) -> -[ 5000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> -[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> -[15000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 784) -> [15000 ps] RD @ (4, 512) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16089) -> [15000 ps] RD @ (4, 504) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15010) -> [15000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> -[15000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12852) -> [10000 ps] ACT @ (4, 11772) -> -[ 5000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> -[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> -[15000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6376) -> [15000 ps] RD @ (4, 496) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5297) -> [15000 ps] RD @ (4, 496) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4218) -> [15000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> -[15000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2060) -> [10000 ps] ACT @ (4, 980) -> -[ 5000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> -[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> -[15000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [15000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11968) -> [15000 ps] RD @ (4, 488) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10889) -> [15000 ps] RD @ (4, 488) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9810) -> [15000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8731) -> -[15000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7651) -> [15000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5493) -> -[10000 ps] ACT @ (0, 4414) -> [ 5000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [15000 ps] RD @ (0, 472) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14323) -> -[15000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13243) -> [15000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11085) -> -[10000 ps] ACT @ (0, 10006) -> [ 5000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [15000 ps] RD @ (0, 464) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3531) -> -[15000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2451) -> [15000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 293) -> -[10000 ps] ACT @ (0, 15598) -> [ 5000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [15000 ps] RD @ (0, 456) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9123) -> -[15000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8043) -> [15000 ps] RD @ (4, 448) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5885) -> [15000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3727) -> [10000 ps] ACT @ (4, 2647) -> [ 5000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> -[15000 ps] RD @ (0, 440) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [15000 ps] RD @ (4, 440) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12556) -> [15000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11477) -> [15000 ps] RD @ (0, 440) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9319) -> [10000 ps] ACT @ (4, 8239) -> [ 5000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> -[15000 ps] RD @ (0, 432) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [15000 ps] RD @ (4, 432) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1764) -> [15000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 685) -> [15000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14911) -> [10000 ps] ACT @ (4, 13831) -> [ 5000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> -[15000 ps] RD @ (0, 424) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [15000 ps] RD @ (4, 424) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7356) -> [15000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6277) -> [15000 ps] RD @ (0, 416) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4118) -> -[15000 ps] RD @ (4, 416) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1960) -> [10000 ps] ACT @ (0, 881) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [15000 ps] RD @ (0, 408) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10790) -> [15000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9710) -> -[15000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7552) -> [10000 ps] ACT @ (0, 6473) -> [ 5000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [15000 ps] RD @ (0, 400) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16382) -> [15000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15302) -> -[15000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13144) -> [10000 ps] ACT @ (0, 12065) -> [ 5000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [15000 ps] RD @ (0, 384) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5590) -> [15000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4510) -> -[15000 ps] RD @ (4, 384) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2352) -> [15000 ps] RD @ (0, 384) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 194) -> [10000 ps] ACT @ (4, 15498) -> [ 5000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (4, 376) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> -[ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> -[15000 ps] RD @ (4, 376) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9023) -> [15000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7944) -> [15000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5786) -> [10000 ps] ACT @ (4, 4706) -> [ 5000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (4, 368) -> [ 7500 ps] NOP -> [20000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3627) -> [15000 ps] RD @ (4, 368) -> -[137500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 2548) -> [15000 ps] RD @ (0, 368) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [25000 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [15000 ps] RD @ (4, 360) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9219) -> -[15000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8140) -> [15000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5982) -> -[10000 ps] ACT @ (4, 4902) -> [ 5000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1665) -> [10000 ps] ACT @ (4, 585) -> [ 5000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> -[15000 ps] RD @ (4, 344) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [15000 ps] RD @ (0, 344) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12653) -> [15000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11573) -> [15000 ps] RD @ (4, 344) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9415) -> [10000 ps] ACT @ (0, 8336) -> [ 5000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> -[15000 ps] RD @ (4, 336) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [15000 ps] RD @ (0, 336) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1861) -> [15000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 781) -> [15000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15007) -> [10000 ps] ACT @ (0, 13928) -> [ 5000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> -[15000 ps] RD @ (4, 328) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [15000 ps] RD @ (0, 328) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7453) -> [15000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6373) -> [15000 ps] RD @ (4, 320) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4215) -> [10000 ps] ACT @ (0, 3136) -> [ 5000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16282) -> [10000 ps] ACT @ (0, 15203) -> [ 5000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [15000 ps] RD @ (4, 312) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10886) -> [15000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9807) -> -[15000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7649) -> [10000 ps] ACT @ (4, 6569) -> [ 5000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> [15000 ps] RD @ (4, 304) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [15000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15399) -> -[15000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13241) -> [10000 ps] ACT @ (4, 12161) -> [ 5000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [15000 ps] RD @ (4, 288) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5686) -> [15000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4607) -> -[15000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2449) -> [10000 ps] ACT @ (4, 1369) -> [ 5000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 280) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14516) -> [10000 ps] ACT @ (4, 13436) -> -[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> -[15000 ps] RD @ (0, 280) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9120) -> [15000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8040) -> [15000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5882) -> [10000 ps] ACT @ (0, 4803) -> [ 5000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 272) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> -[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> -[15000 ps] RD @ (0, 264) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14712) -> [15000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13632) -> [15000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11474) -> [10000 ps] ACT @ (0, 10395) -> [ 5000 ps] RD @ (4, 264) -> -[10000 ps] RD @ (0, 264) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> -[15000 ps] RD @ (0, 256) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3920) -> [15000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2840) -> [15000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 682) -> [10000 ps] ACT @ (0, 15987) -> [ 5000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 248) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> -[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12749) -> -[10000 ps] ACT @ (0, 11670) -> [ 5000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[15000 ps] RD @ (0, 248) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8432) -> [15000 ps] RD @ (4, 248) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7353) -> [15000 ps] RD @ (4, 240) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6274) -> [15000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[15000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4116) -> [10000 ps] ACT @ (4, 3036) -> -[ 5000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> -[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[15000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14024) -> [15000 ps] RD @ (4, 232) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12945) -> [15000 ps] RD @ (4, 232) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11866) -> [15000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[15000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9708) -> [10000 ps] ACT @ (4, 8628) -> -[ 5000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> -[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[15000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3232) -> [15000 ps] RD @ (4, 224) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2153) -> [15000 ps] RD @ (4, 224) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1074) -> [15000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[15000 ps] RD @ (0, 216) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15300) -> [10000 ps] ACT @ (4, 14220) -> -[ 5000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> -[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10983) -> [10000 ps] ACT @ (4, 9903) -> [ 5000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [15000 ps] RD @ (0, 208) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5587) -> -[15000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4507) -> [15000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2349) -> -[10000 ps] ACT @ (0, 1270) -> [ 5000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [15000 ps] RD @ (0, 200) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11179) -> -[15000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10099) -> [15000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7941) -> -[10000 ps] ACT @ (0, 6862) -> [ 5000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> -[10000 ps] NOP -> [ 7500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> -[15000 ps] RD @ (4, 192) -> [107500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 1466) -> -[15000 ps] RD @ (0, 192) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 387) -> [15000 ps] RD @ (0, 192) -> [15000 ps] ACT @ (4, 15691) -> -[15000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13533) -> [10000 ps] ACT @ (0, 12454) -> [ 5000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9216) -> [10000 ps] ACT @ (0, 8137) -> -[ 5000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> -[15000 ps] RD @ (4, 176) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3820) -> [15000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2741) -> [15000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 583) -> [10000 ps] ACT @ (4, 15887) -> [ 5000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (4, 168) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> -[ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> -[15000 ps] RD @ (4, 168) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9412) -> [15000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8333) -> [15000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6175) -> [10000 ps] ACT @ (4, 5095) -> [ 5000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (4, 160) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> -[ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> -[15000 ps] RD @ (4, 152) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15004) -> [15000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13925) -> [15000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> -[27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11767) -> [10000 ps] ACT @ (4, 10687) -> [ 5000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (4, 152) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> -[ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7450) -> -[10000 ps] ACT @ (4, 6370) -> [ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> -[15000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3133) -> [15000 ps] RD @ (0, 144) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2054) -> [15000 ps] RD @ (0, 144) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 974) -> [15000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> -[15000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15200) -> [10000 ps] ACT @ (0, 14121) -> -[ 5000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> -[10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> -[15000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8725) -> [15000 ps] RD @ (0, 136) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7646) -> [15000 ps] RD @ (0, 128) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6566) -> [15000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> -[15000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4408) -> [10000 ps] ACT @ (0, 3329) -> -[ 5000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> -[10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> -[15000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14317) -> [15000 ps] RD @ (0, 120) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13238) -> [15000 ps] RD @ (0, 120) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12158) -> [15000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> -[15000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10000) -> [10000 ps] ACT @ (0, 8921) -> -[ 5000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> -[10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5683) -> [10000 ps] ACT @ (0, 4604) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [15000 ps] RD @ (4, 112) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 287) -> -[15000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15592) -> [15000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13434) -> -[10000 ps] ACT @ (4, 12354) -> [ 5000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [15000 ps] RD @ (4, 96) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5879) -> -[15000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4800) -> [15000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2642) -> -[10000 ps] ACT @ (4, 1562) -> [ 5000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [15000 ps] RD @ (4, 88) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11471) -> -[15000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10392) -> [15000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8234) -> -[10000 ps] ACT @ (4, 7154) -> [ 5000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3917) -> [10000 ps] ACT @ (4, 2837) -> [ 5000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> -[15000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [15000 ps] RD @ (0, 72) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14905) -> [15000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13825) -> [15000 ps] RD @ (4, 72) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11667) -> [10000 ps] ACT @ (0, 10588) -> [ 5000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> -[15000 ps] RD @ (4, 64) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [15000 ps] RD @ (0, 64) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4113) -> [15000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3033) -> [15000 ps] RD @ (4, 64) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 875) -> [10000 ps] ACT @ (0, 16180) -> [ 5000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> -[15000 ps] RD @ (4, 56) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [15000 ps] RD @ (0, 56) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9705) -> [15000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8625) -> [15000 ps] RD @ (4, 56) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6467) -> [10000 ps] ACT @ (0, 5388) -> [ 5000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2150) -> [10000 ps] ACT @ (0, 1071) -> [ 5000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (0, 48) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [15000 ps] RD @ (4, 40) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13138) -> [15000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12059) -> -[15000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9901) -> [10000 ps] ACT @ (4, 8821) -> [ 5000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [15000 ps] RD @ (4, 32) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2346) -> [15000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1267) -> -[15000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15493) -> [10000 ps] ACT @ (4, 14413) -> [ 5000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> -[27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> -[10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [15000 ps] RD @ (4, 24) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7938) -> [15000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6859) -> -[15000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4701) -> [10000 ps] ACT @ (4, 3621) -> [ 5000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> -[ 7500 ps] NOP -> [20000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2542) -> [15000 ps] RD @ (4, 16) -> [137500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 1463) -> [15000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> [15000 ps] ACT @ (4, 15688) -> [15000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13530) -> -[10000 ps] ACT @ (0, 12451) -> [ 5000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> [27500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [15000 ps] RD @ (0, 0) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5976) -> -[15000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4896) -> [15000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2738) -> -[10000 ps] ACT @ (0, 1659) -> [ 5000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> -[15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (0, 13727) -> [10000 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> -[15000 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12647) -> [10000 ps] ACT @ (4, 11568) -> [ 5000 ps] RD @ (3, 1016) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (0, 9410) -> [10000 ps] ACT @ (7, 10488) -> [15000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9409) -> -[15000 ps] RD @ (7, 1016) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (7, 8330) -> -[10000 ps] ACT @ (4, 7251) -> [ 5000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7251) -> [15000 ps] RD @ (3, 1008) -> -[17500 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5092) -> [15000 ps] RD @ (7, 1008) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [15000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> -[15000 ps] RD @ (7, 1008) -> [15000 ps] ACT @ (4, 1855) -> [12500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [12500 ps] PRE @ (4) -> -[ 2500 ps] RD @ (3, 1008) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 15002) -> [10000 ps] ACT @ (7, 16080) -> [15000 ps] RD @ (7, 1000) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [15000 ps] ACT @ (4, 13922) -> [12500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13922) -> -[12500 ps] PRE @ (4) -> [ 2500 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12843) -> [15000 ps] RD @ (3, 1000) -> -[15000 ps] ACT @ (4, 11764) -> [12500 ps] PRE @ (3) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (3, 11764) -> [10000 ps] ACT @ (0, 10685) -> -[ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10684) -> [15000 ps] RD @ (7, 1000) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (7) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (7, 9605) -> [10000 ps] ACT @ (4, 8526) -> [ 5000 ps] RD @ (7, 1000) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8526) -> [15000 ps] RD @ (3, 1000) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> -[15000 ps] RD @ (3, 992) -> [15000 ps] ACT @ (0, 5289) -> [12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5288) -> [12500 ps] PRE @ (0) -> -[ 2500 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 2051) -> [10000 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16277) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16276) -> [15000 ps] RD @ (7, 984) -> -[17500 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14118) -> [15000 ps] RD @ (3, 984) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> -[15000 ps] RD @ (3, 984) -> [15000 ps] ACT @ (0, 10881) -> [12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10880) -> [12500 ps] PRE @ (0) -> -[ 2500 ps] RD @ (7, 984) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> -[15000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6564) -> [10000 ps] ACT @ (7, 5484) -> -[ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> -[10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> -[15000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [17500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 88) -> [15000 ps] RD @ (7, 976) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15393) -> [15000 ps] RD @ (7, 968) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14314) -> [15000 ps] RD @ (3, 968) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13235) -> -[15000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12155) -> [15000 ps] RD @ (7, 968) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9997) -> -[10000 ps] ACT @ (3, 8918) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [15000 ps] RD @ (3, 960) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2443) -> -[15000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1363) -> [15000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15589) -> -[10000 ps] ACT @ (3, 14510) -> [ 5000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [15000 ps] RD @ (3, 952) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8035) -> -[15000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6955) -> [15000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4797) -> -[10000 ps] ACT @ (3, 3718) -> [ 5000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [15000 ps] RD @ (3, 936) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13627) -> -[15000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12547) -> [15000 ps] RD @ (7, 936) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10389) -> [15000 ps] RD @ (3, 936) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 8231) -> [10000 ps] ACT @ (7, 7151) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> -[15000 ps] RD @ (3, 928) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [15000 ps] RD @ (7, 928) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 676) -> [15000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15981) -> [15000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13823) -> [10000 ps] ACT @ (7, 12743) -> [ 5000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> -[15000 ps] RD @ (3, 920) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [15000 ps] RD @ (7, 912) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6268) -> [15000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5189) -> [15000 ps] RD @ (3, 912) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3031) -> [10000 ps] ACT @ (7, 1951) -> [ 5000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> -[15000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [15000 ps] RD @ (7, 904) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11860) -> [15000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10781) -> [15000 ps] RD @ (3, 904) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8622) -> -[15000 ps] RD @ (7, 904) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6464) -> [10000 ps] ACT @ (3, 5385) -> [ 5000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> -[10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [15000 ps] RD @ (3, 888) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15294) -> [15000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14214) -> -[15000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12056) -> [10000 ps] ACT @ (3, 10977) -> [ 5000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [15000 ps] RD @ (3, 880) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4502) -> [15000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3422) -> -[15000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1264) -> [10000 ps] ACT @ (3, 185) -> [ 5000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] NOP -> -[20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [137500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 11173) -> [15000 ps] RD @ (3, 872) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10094) -> -[15000 ps] RD @ (3, 872) -> [15000 ps] ACT @ (7, 9014) -> [15000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7935) -> -[15000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6856) -> [15000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4698) -> -[10000 ps] ACT @ (7, 3618) -> [ 5000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [15000 ps] RD @ (7, 856) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13527) -> -[15000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12448) -> [15000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10290) -> -[10000 ps] ACT @ (7, 9210) -> [ 5000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [15000 ps] RD @ (7, 848) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> -[15000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1656) -> [15000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15882) -> -[10000 ps] ACT @ (7, 14802) -> [ 5000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [15000 ps] RD @ (7, 840) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8327) -> -[15000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7248) -> [15000 ps] RD @ (3, 832) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5089) -> [15000 ps] RD @ (7, 832) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2931) -> [10000 ps] ACT @ (3, 1852) -> [ 5000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> -[15000 ps] RD @ (7, 824) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [15000 ps] RD @ (3, 824) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11761) -> [15000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10681) -> [15000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8523) -> [10000 ps] ACT @ (3, 7444) -> [ 5000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> -[15000 ps] RD @ (7, 816) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [15000 ps] RD @ (3, 816) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 969) -> [15000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 16273) -> [15000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 14115) -> [10000 ps] ACT @ (3, 13036) -> [ 5000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> -[15000 ps] RD @ (7, 808) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [15000 ps] RD @ (3, 800) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6561) -> [15000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5481) -> [15000 ps] RD @ (7, 800) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3323) -> -[15000 ps] RD @ (3, 800) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1165) -> [10000 ps] ACT @ (7, 85) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> -[27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [15000 ps] RD @ (7, 792) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9994) -> [15000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8915) -> -[15000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6757) -> [10000 ps] ACT @ (7, 5677) -> [ 5000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> -[27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [15000 ps] RD @ (7, 784) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15586) -> [15000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14507) -> -[15000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12349) -> [10000 ps] ACT @ (7, 11269) -> [ 5000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> -[27500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6953) -> -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 141060000 ps -Time Done: 272360000 ps -Diff: 131_300 ns (57 ns/req) - -[15000 ps] RD @ (3, 768) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [15000 ps] RD @ (7, 768) -> -FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 272420000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 273460 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 452 -run: Time (s): cpu = 00:16:40 ; elapsed = 00:49:14 . Memory (MB): peak = 8221.426 ; gain = 5.004 ; free physical = 1649 ; free virtual = 23979 - diff --git a/temp_new.log b/temp_new.log deleted file mode 100644 index 650c125..0000000 --- a/temp_new.log +++ /dev/null @@ -1,12065 +0,0 @@ -relaunch_sim -INFO: xsimkernel Simulation Memory Usage: 305668 KB (Peak: 371204 KB), Simulation CPU Usage: 2656450 ms -Command: launch_simulation -step compile -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-2] XSim::Compile design -INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xvlog --incr --relax -L uvm -prj ddr3_dimm_micron_sim_vlog.prj -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Waiting for jobs to finish... -No pending jobs, compilation finished. -INFO: [USF-XSim-69] 'compile' step finished in '3' seconds -Command: launch_simulation -step elaborate -simset sim_1 -mode behavioral -INFO: [Vivado 12-12493] Simulation top is 'ddr3_dimm_micron_sim' -WARNING: [Vivado 12-12986] Compiled library path does not exist: '' -INFO: [Vivado 12-5682] Launching behavioral simulation in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -INFO: [SIM-utils-51] Simulation object is 'sim_1' -INFO: [USF-XSim-3] XSim::Elaborate design -INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/home/angelo/Desktop/switch_fpga/switch_fpga.sim/sim_1/behav/xsim' -xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim_behav xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Using 8 slave threads. -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:201] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:132] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:153] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:154] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:155] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:162] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:247] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:272] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:273] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:278] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:280] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:316] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:322] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:323] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:371] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:372] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:423] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:424] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:449] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:450] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:455] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:457] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:494] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:495] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:496] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:503] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:533] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:572] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:573] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:577] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:579] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:628] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:629] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:697] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:698] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:744] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim_behav -run_program: Time (s): cpu = 00:02:50 ; elapsed = 00:01:47 . Memory (MB): peak = 8185.504 ; gain = 0.000 ; free physical = 1319 ; free virtual = 24393 -INFO: [USF-XSim-69] 'elaborate' step finished in '107' seconds -launch_simulation: Time (s): cpu = 00:02:50 ; elapsed = 00:01:47 . Memory (MB): peak = 8185.504 ; gain = 0.000 ; free physical = 1319 ; free virtual = 24393 -Time resolution is 1 ps -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> run: Time (s): cpu = 00:00:01 ; elapsed = 00:00:09 . Memory (MB): peak = 8185.504 ; gain = 0.000 ; free physical = 1261 ; free virtual = 24261 -relaunch_xsim_kernel: Time (s): cpu = 00:00:02 ; elapsed = 00:00:10 . Memory (MB): peak = 8185.504 ; gain = 0.000 ; free physical = 1261 ; free virtual = 24261 -relaunch_sim: Time (s): cpu = 00:47:03 ; elapsed = 00:02:01 . Memory (MB): peak = 8185.504 ; gain = 0.000 ; free physical = 1261 ; free virtual = 24261 -run all -[370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[237500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43461402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43463902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43466402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43468902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43471402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43476402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43611480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43613980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43616480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43618980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43621480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43626480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45712600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45715100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45717600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45720100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45722600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45725100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45727600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45730100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46311402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46313902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46316402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46318902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46321402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46323902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46326402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46328902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46461480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46463980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46466480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46468980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46471480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46473980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46476480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46478980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48562600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48565100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48567600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48570100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49161402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49163902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49166402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49168902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49171402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49173902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49176402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49178902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49311480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49313980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49316480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49318980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49321480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49323980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49326480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49328980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51412600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51415100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51417600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51420100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52011402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52013902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52016402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52018902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52021402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52023902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52026402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52028902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52161480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52163980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52166480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52168980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52171480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52173980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52176480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52178980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54262600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54265100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54267600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54270100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54861402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54863902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54866402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54868902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54871402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54873902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54876402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54878902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55011480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55013980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55016480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55018980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55021480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55023980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55026480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55028980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57112600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57115100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57117600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57120100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57711402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57713902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57716402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57718902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57721402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57723902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57726402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57728902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57861480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57863980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57866480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57868980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57871480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57873980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57876480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57878980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59962600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59965100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59967600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59970100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60411350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60413850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60416350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60418850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60561350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60561402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60563850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60563902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60566350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60566402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60568850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60568902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60571402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60573902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60576402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60578902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60711350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60711480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60713850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60713980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60716350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60716480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60718850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60718980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60721480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60723980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60726480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60728980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60861350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60863850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60866350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60868850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61011350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61013850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61016350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61018850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61161350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61163850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61166350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61168850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61311350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61313850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61316350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61318850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61461350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61463850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61466350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61468850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61611350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61613850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61616350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61618850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61761350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61763850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61766350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61768850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61911350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61913850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61916350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61918850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62061350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62063850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62066350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62068850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62211350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62213850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62216350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62218850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62361350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62363850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62366350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62368850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62511350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62513850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62516350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62518850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62661350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62663850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62666350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62668850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62811350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62812600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62813850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62815100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62816350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62817600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62818850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62820100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62961350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62962650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62963850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62965150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62966350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62967650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62968850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62970150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63111350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63112650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63113850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63115150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63116350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63117650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63118850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63120150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63261350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63262650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63263850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63265150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63266350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63267650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63268850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63270150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63411402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63412650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63413902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63415150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63416402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63417650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63418902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63420150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63421402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63423902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63426402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63428902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63561480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63562650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63563980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63565150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63566480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63567650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63568980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63570150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63571480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63573980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63576480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63578980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63712650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63715150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63717650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63720150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63862650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63865150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63867650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63870150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64012650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64015150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64017650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64020150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64162650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64165150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64167650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64170150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64312650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64315150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64317650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64320150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64462650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64465150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64467650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64470150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64612650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64615150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64617650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64620150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64762650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64765150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64767650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64770150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64912650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64915150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64917650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64920150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65062650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65065150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65067650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65070150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65212650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65215150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65217650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65220150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65362650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65365150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65367650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65370150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65512600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65512650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65515100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65515150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65517600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65517650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65520100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65520150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65522600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65525100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65527600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65530100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65662600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65662650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65665100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65665150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65667600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65667650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65670100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65670150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65812650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65815150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65817650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65820150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[22660000 ps] MRS -> -[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 0) -> -[17500 ps] WR @ (0, 0) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> -[10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> -[10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> -[10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> -[10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> -[10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> -[10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> -[10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> -[10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> -[10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> -[10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> -[10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> -[10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> -[10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> -[10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> -[10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> -[10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> -[10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> -[10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> -[10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> -[10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> -[10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> -[10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> -[10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> -[10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> -[10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> -[10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> -[10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> -[10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> -[10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> -[10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> -[10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> -[10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> -[10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> -[10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> -[10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> -[10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> -[10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> -[10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> -[10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> -[10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> -[10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> -[10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> -[10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> -[10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> -[10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> -[10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> -[10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> -[10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> -[10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> -[10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> -[10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> -[10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> -[10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> -[10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> -[10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> -[10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> -[10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> -[10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> -[10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> -[10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> -[10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> -[10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> -[10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> -[10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> -[10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> -[10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> -[10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> -[10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> -[10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> -[10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> -[10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> -[10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> -[10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> -[10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> -[10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> -[10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> -[10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> -[10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> -[10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> -[10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> -[10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> -[10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> -[10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> -[10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> -[10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> -[10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> -[10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> -[10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> -[10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> -[10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> -[10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> -[10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> -[10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> -[10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> -[10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> -[10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> -[10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> -[10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> -[10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> -[10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> -[10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> -[ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> -[10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> -[10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> -[10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> -[10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> -[10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> -[10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> -[10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> -[10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> -[10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> -[10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> -[10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> -[10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> -[10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> -[10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> -[10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> -[10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> -[10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> -[10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> -[10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> -[10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> -[10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> -[10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> -[10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> -[ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [165000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> -[10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> -[ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> -[10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> -[10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> -[10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> -[10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> -[10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> -[10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> -[10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> -[10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> -[10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> -[10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> -[10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> -[10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> -[10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> -[10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> -[10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> -[10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> -[10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> -[10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> -[10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> -[10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> -[10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> -[10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> -[10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> -[10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> -[10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> -[10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> -[10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> -[10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> -[10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> -[10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> -[10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> -[10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> -[10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> -[10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> -[10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> -[10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> -[10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> -[10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> -[10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> -[10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> -[10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> -[10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> -[10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> -[10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> -[10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> -[10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> -[10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> -[10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> -[10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> -[10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> -[10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> -[10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> -[15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -[ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -[10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> -[10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> -[10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> -[10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> -[10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> -[10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> -[10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> -[10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> -[10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> -[10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> -[10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> -[10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> -[10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> -[10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> -[10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> -[10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> -[10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> -[10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> -[10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> -[10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> -[10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> -[10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> -[10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> -[10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> -[10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> -[10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> -[10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> -[10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> -[10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> -[10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> -[10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> -[10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> -[10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> -[10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> -[10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> -[10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> -[10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> -[10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> -[10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> -[10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> -[10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> -[10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> -[10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> -[10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> -[10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> -[10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> -[10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> -[10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> -[10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> -[10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (2, 0) -> -[15000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> -[10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> -[10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> -[10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> -[10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> -[10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> -[10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> -[10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> -[10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> -[10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> -[10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> -[10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> -[10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> -[10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> -[10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> -[10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> -[10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> -[10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> -[10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> -[10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> -[10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> -[10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> -[10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> -[10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> -[10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> -[ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> -[10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> -[10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> -[10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> -[10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> -[10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> -[10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> -[10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> -[10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> -[10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> -[10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> -[10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> -[10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> -[10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> -[10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> -[10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> -[ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> -[10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> -[10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> -[10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> -[10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> -[10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> -[10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> -[10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> -[10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> -[10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> -[10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> -[10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> -[10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> -[10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> -[10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> -[10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> -[10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> -[10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> -[10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> -[10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> -[10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> -[10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> -[10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> -[10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> -[10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> -[10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> -[10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> -[10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> -[10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> -[10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> -[10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> -[10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> -[10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> -[10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> -[10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> -[10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> -[10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> -[10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> -[10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> -[10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> -[10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> -[10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> -[10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> -[10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> -[10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> -[10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> -[10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> -[10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> -[10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> -[10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> -[10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> -[10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> -[10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> -[10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> -[10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> -[10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> -[10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> -[10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> -[10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> -[10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> -[10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> -[10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> -[10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> -[10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> -[10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> -[10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> -[10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> -[10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> -[10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> -[10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> -[10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> -[10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> -[10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> -[10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> -[10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> -[10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> -[10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> -[10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> -[10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 66610000 ps -Time Done: 90920000 ps - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 91000000.0 ps -[190000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [37500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8192) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> -[10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> -[10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> -[10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> -[10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> -[10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> -[10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> -[10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> -[10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> -[10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> -[10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> -[10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> -[10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> -[10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> -[10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> -[10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> -[10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> -[10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> -[10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> -[10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> -[10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> -[10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> -[10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> -[10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> -[10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> [ 7500 ps] WR @ (1, 976) -> -[10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> -[10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> -[10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> -[10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> -[10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> -[10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> -[10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> -[10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> -[10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> -[10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> -[10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> -[10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> -[10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> -[10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> -[10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> -[10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> -[10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> -[10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> -[10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> -[10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> -[10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> -[10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> -[10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> -[10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> -[10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> -[10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> -[10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> -[10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> -[10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> -[10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> -[10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> -[10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> -[10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> -[10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> -[10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> -[10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> -[10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> -[10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> -[10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> -[10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> -[10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> -[10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> -[10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> -[10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> -[10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> -[10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> -[10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> -[10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> -[10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> -[10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> -[10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> -[10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> -[10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> -[10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> -[10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> -[10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> -[10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> -[10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> -[10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> -[10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> -[10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> -[10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> -[10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> -[10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> -[10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> -[10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> -[10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> -[10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> -[10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> -[10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> -[10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> -[10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> -[10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> -[10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> -[10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> -[10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> -[10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> -[ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> -[10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> -[10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> -[10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> -[10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> -[10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> -[10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> -[10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> -[10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> -[10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> -[10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> -[10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> -[10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> -[10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> -[10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> -[10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> -[10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> -[10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> -[10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> -[10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> -[10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> -[10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> -[10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> -[10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> -[10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> -[10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 8192) -> -[ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> -[10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> -[10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> -[10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> -[10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> -[10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> -[10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> -[10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> -[10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> -[10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> -[10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> -[10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> -[10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> -[10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> -[10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> -[10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> -[10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> -[10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> -[10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> -[10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> -[10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> -[10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> -[10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> -[10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> -[10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> [ 7500 ps] WR @ (6, 976) -> -[10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> -[10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> -[10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> -[10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> -[10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> -[10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> -[10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> -[10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> -[10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> -[10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> -[10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> -[10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> -[10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> -[10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> -[10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> -[10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> -[10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> -[10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> -[10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> -[10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> -[10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> -[10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> -[10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> -[10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> -[10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> -[10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> -[10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> -[15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -[ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -[10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> -[10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> -[10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> -[10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> -[10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> -[10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> -[10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> -[10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> -[10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> -[10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> -[10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> -[10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> -[10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> -[10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> -[10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> -[10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> -[10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> -[10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> -[10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> -[10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> -[10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> -[10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> -[10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> -[10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> -[10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> -[10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> -[10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> -[10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> -[10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> -[10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> -[10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> -[10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> -[10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> -[10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> -[10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> -[10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> -[10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> -[10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> -[10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> -[10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> -[10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> -[10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> -[10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> -[10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> -[10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> -[10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> -[10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> -[10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> -[10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> -[10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> -[10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> -[10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> -[10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> -[10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> -[10000 ps] RD @ (3, 96) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[167500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 128) -> -[10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> -[10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> -[10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> -[10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> -[10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> -[10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> -[10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> -[10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> -[10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> -[10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> -[10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> -[10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> -[10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> -[10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> -[10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> -[10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> -[10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> -[10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> -[10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> -[10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> -[ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> -[10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> -[10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> -[10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> -[10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> -[10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> -[10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> -[10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> -[10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> -[10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> -[10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> -[10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> -[10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> -[10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> -[10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> -[10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 8192) -> -[ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> -[10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> -[10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> -[10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> -[10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> -[10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> -[10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> -[10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> -[10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> -[10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> -[10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> -[10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> -[10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> -[10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> -[10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> -[10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> -[10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> -[10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> -[10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> -[10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> -[10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> -[10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> -[10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> -[10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> -[10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> -[10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> [ 5000 ps] RD @ (5, 976) -> -[10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> -[10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> -[10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> -[10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> -[10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> -[10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> -[10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> -[10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> -[10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> -[10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> -[10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> -[10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> -[10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> -[10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> -[10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> -[10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> -[10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> -[10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> -[10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> -[10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> -[10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> -[10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> -[10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> -[10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> -[10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> -[10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> -[10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> -[10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> -[10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> -[10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> -[10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> -[10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> -[10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> -[10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> -[10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> -[10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> -[10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> -[10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> -[10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> -[10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> -[10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> -[10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> -[10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> -[10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> -[10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> -[10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> -[10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> -[10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> -[10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> -[10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> -[10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> -[10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> -[10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 91020000 ps -Time Done: 115860000 ps - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 115940000.0 ps -[107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[165000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> -[10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> -[10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> -[10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> -[10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> -[10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> -[10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> -[10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> -[10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> -[10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> -[10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> -[10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> -[10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> -[10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> -[10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> -[10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> -[10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> -[10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> -[10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> -[10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> -[10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> -[10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> -[10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> -[10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> -[10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> -[ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> -[10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> -[10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> -[10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> -[10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> -[10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> -[10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> -[10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> -[10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> -[10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> -[10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> -[10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> -[10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> -[10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> -[10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> -[10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> -[10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> -[10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> -[10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> -[10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> -[10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> -[10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> -[10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> -[10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> -[10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> -[10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> -[ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> -[10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> -[10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> -[10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> -[10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> -[10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> -[10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> -[10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> -[10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> -[10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> -[10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> -[10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> -[10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> -[10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> -[10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> -[10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> -[10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> -[10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> -[10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> -[10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> -[10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> -[10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> -[10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> -[10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> -[10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> -[10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> -[10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> -[10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> -[10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> -[10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> -[10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> -[10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> -[10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> -[10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> -[10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> -[10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> -[10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> -[10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> -[10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> -[10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> -[10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> -[10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> -[10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> -[10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> -[10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> -[10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> -[10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> -[10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> -[10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> -[10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> -[10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> -[10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> -[10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> -[10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> -[10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> -[10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> -[10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> -[10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> -[10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> -[10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> -[10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> -[10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> -[10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> -[10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> -[10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> -[10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> -[10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> -[10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> -[10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> -[10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> -[10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> -[10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> -[10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> -[10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> -[10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> -[10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> -[10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> -[10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> -[10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> -[10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> -[10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> -[10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [165000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (6, 16383) -> -[17500 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> -[10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> -[10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> -[10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> -[10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> -[10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> -[10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> -[10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> -[10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> -[10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> -[10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> -[10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> -[10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> -[10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> -[10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> -[10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> -[10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> -[10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> -[10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> -[ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> -[10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> -[10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> -[10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> -[10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> -[10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> -[10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> -[10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> -[10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> -[10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> -[10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> -[10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> -[10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> -[10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> -[10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> -[10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> -[10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> -[10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> -[10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> -[10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> -[10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> -[10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> -[10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> -[10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> -[10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> -[10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> -[ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> -[10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> -[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> -[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> -[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> -[10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> -[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> -[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> -[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> -[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> -[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> -[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> -[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> -[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> -[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> -[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> -[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> -[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> -[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> -[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> -[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> -[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> -[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> -[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> -[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> -[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> -[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> -[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> -[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> -[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> -[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> -[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> -[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> -[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> -[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> -[ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> -[10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> -[10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> -[10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> -[10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> -[10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> -[10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> -[10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> -[10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> -[10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> -[10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> -[10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> -[10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> -[10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> -[10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> -[10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> -[10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> -[10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> -[10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> -[10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> -[10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> -[10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> -[10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> -[10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> -[10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> -[ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> -[10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> -[10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> -[10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> -[10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> -[10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> -[10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> -[10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> -[10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> -[10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> -[10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> -[10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> -[10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> -[10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> -[10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> -[10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> -[10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> -[10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> -[10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> -[10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> -[10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> -[10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> -[10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> -[10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> -[10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> -[10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> -[10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> -[10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> -[10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> -[10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> -[10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> -[10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> -[10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [167500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> -[10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> -[10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> -[10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> -[10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> -[10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> -[10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> -[10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> -[10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> -[10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> -[10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> -[10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> -[10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> -[10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> -[10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> -[10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> -[10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> -[10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> -[10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> -[10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> -[10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> -[10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> -[10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> -[10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> -[10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> -[10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> -[10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> -[10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> -[10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> -[10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> -[10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> -[10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> -[10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> -[10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> -[10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> -[10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> -[10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> -[10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> -[10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> -[10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> -[10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> -[10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> -[10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> -[10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> -[10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> -[10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> -[10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> -[10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> -[10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> -[10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> -[10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> -[10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> -[10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> -[10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> -[10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> -[10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> -[10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> -[10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> -[ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> -[10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> -[10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> -[10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> -[10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> -[10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> -[10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> -[10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> -[10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> -[10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> -[10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> -[10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> -[10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> -[10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> -[10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> -[10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> -[10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> -[10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> -[10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> -[10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> -[10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> -[10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> -[10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> -[10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> -[10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> -[10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> -[ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> -[10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> -[10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> -[10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> -[10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> -[10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> -[10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> -[10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> -[10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> -[10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> -[10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> -[10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> -[10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> -[10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> -[10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> -[10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> -[10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> -[10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> -[10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> -[10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> -[10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> -[10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> -[10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> -[10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> -[10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> -[10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> -[10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> - -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 115960000 ps -Time Done: 140870000 ps -Diff: 24_910 ns (10.8 ns/req) - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 140950000.0 ps -[97500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> -[10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 952) -> -[15000 ps] NOP -> [20000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) -> -[17500 ps] WR @ (0, 952) -> [10000 ps] WR @ (4, 952) -> [115000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [ 2500 ps] ACT @ (0, 7365) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> -[17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5206) -> -[10000 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> -[17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> -[17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> -[10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> -[17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> -[17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> -[10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> -[17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> -[17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> -[10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> -[17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> -[17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> -[10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> -[10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> -[10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> -[10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> -[10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> -[10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> -[10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> -[10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> -[17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> -[10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> -[17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> -[10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> -[17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> -[10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> -[17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> -[10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> -[17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> -[10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> -[17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> -[10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> -[17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [135000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (4, 8245) -> [10000 ps] ACT @ (0, 7166) -> [ 7500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> -[10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> -[10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> -[10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> -[10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> -[10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> -[10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> -[10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> -[17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> -[10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> -[17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> -[10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> -[17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> -[10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> -[17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> -[10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> -[17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> -[10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> -[17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> -[10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> -[17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> -[10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> -[17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> -[17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> -[10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> -[17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> -[17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> -[10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> -[17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> -[17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> -[10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> -[17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> -[17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> -[10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> -[17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [12500 ps] NOP -> [10000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [135000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 7500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> -[10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> -[10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> -[17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> -[17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> -[10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> -[17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> -[10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> -[17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> -[17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> -[10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> -[10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> -[10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> -[17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> -[17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> -[10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> -[17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> -[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> -[10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> -[25000 ps] NOP -> [20000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [55000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 4610) -> [17500 ps] WR @ (0, 464) -> [ 2500 ps] ACT @ (4, 2451) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3531) -> -[17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> -[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> -[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> -[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> -[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> -[10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> -[17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> -[17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> -[10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> -[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> -[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> -[10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> -[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> -[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> -[10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> -[17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> -[17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> -[10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> -[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> -[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> -[10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> -[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> -[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> -[10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> -[10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> -[10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> -[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> -[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> -[10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> -[10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> -[10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> -[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> -[10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> -[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> -[10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> -[17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [145000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [ 2500 ps] ACT @ (4, 1173) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> -[17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15399) -> -[10000 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> -[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> -[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> -[10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> -[17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> -[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> -[10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> -[10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> -[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> -[17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> -[17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> -[10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> -[17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [12500 ps] NOP -> [10000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [135000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [27500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> [ 7500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> -[10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> -[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> -[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> -[10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> -[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> -[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> -[10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> -[17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> -[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> -[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> -[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> -[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> -[10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> -[17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> -[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> -[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> -[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> -[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> -[10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> -[17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> -[10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> -[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> -[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> -[10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> -[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> -[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> -[10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> -[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> -[17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> -[10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> -[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> -[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> -[10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> -[17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> -[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> -[10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> -[17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> -[17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> -[10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> -[17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> -[15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> -[17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> -[ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> -[17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> -[ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> -[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> -[ 5000 ps] NOP -> [30000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> -[17500 ps] WR @ (7, 1008) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U2.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U3.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U4.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U6.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U7.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U8.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -ddr3_dimm_micron_sim.ddr3_dimm.U9.chk_err: at time 191855100.0 ps ERROR: tWR violation during Precharge to bank 7 -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 1855) -> [10000 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> -[ 2500 ps] ACT @ (0, 16081) -> [42500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> [ 2500 ps] ACT @ (7, 16080) -> -[ 2500 ps] PRE @ (0) -> [15000 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> -[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 2500 ps] ACT @ (0, 10685) -> [42500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> -[17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> -[ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> -[17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> -[ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> -[17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> -[17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> -[ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> -[17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> -[ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> -[17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> -[17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> -[ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> -[17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> -[ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> -[17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> -[17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> -[ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> -[17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> [10000 ps] WR @ (7, 952) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> -[10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 928) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> -[10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> -[10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 920) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> -[10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> -[10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> [10000 ps] WR @ (7, 912) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> -[10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> -[10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> -[17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> -[10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> [10000 ps] ACT @ (3, 4306) -> -[17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> -[10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> -[17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> -[10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> [10000 ps] ACT @ (3, 9898) -> -[17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> -[10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> -[17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> -[10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> [10000 ps] ACT @ (3, 15490) -> -[17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> -[10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> -[17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> -[10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> -[17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> -[17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1460) -> -[10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> -[17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> -[17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> -[10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> -[17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> -[17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [15000 ps] NOP -> [20000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [115000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [ 2500 ps] ACT @ (7, 3814) -> -[42500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1656) -> [10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 840) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> -[10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> [10000 ps] WR @ (3, 832) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> -[10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> -[10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 816) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> -[10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> -[10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 808) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> -[10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> -[10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> -[17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> -[10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> [10000 ps] ACT @ (7, 15390) -> -[17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> -[10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> -[17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> -[10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> [10000 ps] ACT @ (7, 4598) -> -[17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> -[10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> -[17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> -[10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> [10000 ps] ACT @ (7, 10190) -> -[17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> -[ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> -[ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [15000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 952) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> [ 5000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> [10000 ps] RD @ (0, 944) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> [ 5000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> -[10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 928) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> [ 5000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> -[15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> [10000 ps] ACT @ (0, 8836) -> -[ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [15000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> -[ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> [10000 ps] ACT @ (0, 14428) -> -[ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [15000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> -[ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> [10000 ps] ACT @ (0, 3636) -> -[ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [15000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> -[ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> -[10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> -[15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> -[15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8149) -> -[10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> -[15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> -[15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> -[10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> -[15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> -[15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13741) -> -[10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> -[15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> -[15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> -[10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> -[15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> -[15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2949) -> -[10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> -[15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> -[15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> -[10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [157500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 5000 ps] ACT @ (4, 2065) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> -[10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> -[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> -[ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> -[ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> -[ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> -[ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> -[ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> -[ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> -[10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> -[15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> -[15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> -[10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> -[15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> -[15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> -[10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> -[15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> -[15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> -[10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> -[15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> -[15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> -[10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> -[15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> -[15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> -[10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> -[15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> -[15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> -[10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> -[10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> -[10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [12500 ps] NOP -> [ 2500 ps] RD @ (0, 632) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 624) -> [117500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (4, 6967) -> -[10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> -[15000 ps] RD @ (0, 624) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> -[15000 ps] RD @ (0, 624) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1571) -> -[10000 ps] ACT @ (0, 492) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [15000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 536) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> [ 5000 ps] RD @ (0, 536) -> -[10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> [10000 ps] RD @ (0, 528) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> [ 5000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> [ 5000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> -[15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> [10000 ps] ACT @ (0, 4022) -> -[ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> [10000 ps] ACT @ (0, 15010) -> -[ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [15000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> [10000 ps] ACT @ (0, 9614) -> -[ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [15000 ps] RD @ (0, 504) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> [10000 ps] ACT @ (0, 4218) -> -[ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [15000 ps] RD @ (0, 496) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [15000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> [10000 ps] ACT @ (0, 15206) -> -[ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [15000 ps] RD @ (0, 488) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [15000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> [10000 ps] ACT @ (0, 9810) -> -[ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> -[10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> -[15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> -[15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3335) -> -[10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> -[15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> -[15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14323) -> -[10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> -[15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> -[15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8927) -> -[10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> -[15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> -[15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3531) -> -[10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> -[15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> -[15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14519) -> -[10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> -[15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> -[15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9123) -> -[10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> [10000 ps] RD @ (4, 416) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [12500 ps] NOP -> [ 2500 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10790) -> [15000 ps] RD @ (0, 408) -> [127500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 9710) -> [15000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[15000 ps] RD @ (4, 408) -> [ 5000 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> -[ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> -[10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> -[ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> -[10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> -[15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> -[15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> -[10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> -[15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> -[15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> -[10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) -> -[10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> -[10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> -[15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> -[15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) -> -[10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> -[15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> -[15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> -[10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> -[15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) -> -[ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) -> -[ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> -[10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> -[15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) -> -[10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> -[15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) -> -[10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> -[15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) -> -[10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) -> -[10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> -[15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) -> -[10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [ 7500 ps] NOP -> [20000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> -[77500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 12454) -> [15000 ps] RD @ (0, 184) -> -[ 5000 ps] ACT @ (4, 10295) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11375) -> [15000 ps] RD @ (0, 184) -> [10000 ps] RD @ (4, 184) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9216) -> [10000 ps] ACT @ (0, 8137) -> [ 5000 ps] RD @ (4, 184) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4899) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> -[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> -[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> -[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> -[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> -[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> -[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> -[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> -[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> -[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> -[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> -[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> -[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> -[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> -[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> -[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> -[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [ 2500 ps] NOP -> [12500 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8526) -> -[15000 ps] RD @ (3, 1000) -> [137500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 7447) -> -[10000 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> -[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (7, 5288) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 992) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3130) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 5000 ps] RD @ (3, 992) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 2051) -> [10000 ps] ACT @ (4, 972) -> [ 5000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> -[15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> -[10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> -[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> -[15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> -[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> -[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> -[10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> -[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> -[ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> -[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> -[10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> -[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> -[ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> -[10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> -[15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> -[15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> -[10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> -[15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> -[15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> -[10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> -[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> -[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> -[10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> -[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> -[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> -[10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> -[15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> -[15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> -[10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> -[15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> -[15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> -[10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> -[10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> -[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> -[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> -[15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> -[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> -[10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> -[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> -[ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [12500 ps] NOP -> -[ 2500 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [117500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[27500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> - -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 140970000 ps -Time Done: 251260000 ps -Diff: 110_290 ns (19% lower) (48 ns/ req) - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 251390000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 252360 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 452 -run: Time (s): cpu = 00:15:06 ; elapsed = 00:45:55 . Memory (MB): peak = 8192.414 ; gain = 6.910 ; free physical = 1014 ; free virtual = 24315 - diff --git a/xsim/.sim.py.swp b/xsim/.sim.py.swp deleted file mode 100644 index 7b69021..0000000 Binary files a/xsim/.sim.py.swp and /dev/null differ diff --git a/xsim/sim_busdelay0.log b/xsim/sim_busdelay0.log deleted file mode 100644 index e69de29..0000000 diff --git a/xsim/sim_busdelay0_flybydelay0.log b/xsim/sim_busdelay0_flybydelay0.log deleted file mode 100644 index 6986bec..0000000 --- a/xsim/sim_busdelay0_flybydelay0.log +++ /dev/null @@ -1,14289 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301324.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 812600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> [370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[247500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43471402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43476402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43481402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43483902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43486402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43488902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43491402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43493902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43621480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43626480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43631480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43633980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43636480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43638980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43641480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43643980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45582600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45585100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45587600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45590100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45592600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45595100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45722600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45725100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45727600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45730100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45732600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45735100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45737600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45740100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45742600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 45745100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46321402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46323902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46326402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46328902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46331402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46333902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46336402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46338902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46341402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46343902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46471480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46473980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46476480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46478980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46481480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46483980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46486480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46488980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46491480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46493980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48432600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48435100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48437600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48440100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48442600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48445100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48572600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48575100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48577600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48580100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48582600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48585100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48587600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48590100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48592600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 48595100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 48893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49171402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49173902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49176402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49178902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49181402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49183902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49186402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49188902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49191402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49193902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49321480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49323980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49326480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49328980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49331480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49333980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49336480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49338980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49341480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49343980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 50993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51282600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51285100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51287600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51290100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51292600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51295100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51422600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51425100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51427600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51430100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51432600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51435100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51437600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51440100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51442600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 51445100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 51893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 51895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52021402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52023902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52026402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52028902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52031402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52033902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52036402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52038902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52041402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52043902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52171480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52173980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52176480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52178980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52181480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52183980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52186480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52188980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52191480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 52193980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 52943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 53993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54132600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54135100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54137600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54140100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54142600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54145100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54272600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54275100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54277600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54280100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54282600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54285100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54287600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54290100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54292600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54295100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54871402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54873902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54876402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54878902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54881402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54883902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54886402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54888902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54891402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 54893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 54893902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 54895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55021480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55023980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55026480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55028980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55031480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55033980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55036480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55038980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55041480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 55043980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 55943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56982600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56985100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56987600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56990100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56992600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 56993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 56995100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 56995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57122600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57125100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57127600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57130100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57132600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57135100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57137600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57140100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57142600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 57145100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57721402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57723902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57726402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57728902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57731402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57733902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57736402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57738902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57741402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57743902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57871480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57873980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57876480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57878980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57881480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57883980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57886480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57888980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57891480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 57893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 57893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 57893980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 57895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 58943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 58943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 58945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59832600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59835100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59837600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59840100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59842600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59845100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59972600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59975100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59977600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59980100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59982600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59985100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59987600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59990100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59992600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 59993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 59993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 59995100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60421350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60423850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60426350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60428850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60431350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60433850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60436350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60438850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60441350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 60443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60443850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60571350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60571402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60573850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60573902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60576350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60576402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60578850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60578902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60581350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60581402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60583850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60583902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60586350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60586402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60588850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60588902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60591350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60591402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60593850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60593902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60721350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60721480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60723850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60723980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60726350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60726480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60728850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60728980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60731350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60731480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60733850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60733980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60736350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60736480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60738850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60738980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60741350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60741480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60743850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 60743980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60871350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60873850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60876350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60878850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60881350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60883850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60886350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60888850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60891350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 60893850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 60895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61021350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61023850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61026350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61028850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61031350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61033850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61036350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61038850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61041350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61043850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61171350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61173850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61176350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61178850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61181350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61183850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61186350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61188850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61191350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61193850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61321350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61323850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61326350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61328850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61331350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61333850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61336350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61338850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61341350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61343850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61471350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61473850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61476350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61478850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61481350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61483850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61486350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61488850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61491350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61493850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61621350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61623850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61626350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61628850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61631350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61633850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61636350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61638850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61641350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61643850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61771350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61773850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61776350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61778850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61781350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61783850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61786350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61788850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61791350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61793850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61921350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61923850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61926350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61928850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61931350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61933850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61936350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61938850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61941350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 61943850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 61945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62071350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62073850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62076350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62078850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62081350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62083850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62086350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62088850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62091350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62093850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62221350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62223850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62226350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62228850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62231350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62233850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62236350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62238850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62241350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62243850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62371350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62373850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62376350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62378850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62381350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62383850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62386350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62388850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62391350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62393850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62521350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62523850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62526350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62528850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62531350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62533850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62536350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62538850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62541350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62543850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62671350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62673850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62676350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62678850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62681350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62682600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62683850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62685100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62686350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62687600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62688850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62690100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62691350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62692600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62693850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62695100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62821350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62822600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62823850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62825100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62826350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62827600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62828850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62830100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62831350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62832600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62833850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62835100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62836350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62837600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62838850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62840100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62841350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62842600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62843850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 62845100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62971350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62972650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62973850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62975150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62976350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62977650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62978850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62980150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62981350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62982650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62983850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62985150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62986350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62987650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62988850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62990150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62991350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62992650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 62993850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 62995150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63121350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63122650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63123850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63125150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63126350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63127650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63128850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63130150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63131350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63132650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63133850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63135150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63136350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63137650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63138850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63140150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63141350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63142650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63143850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63145150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63271350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63272650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63273850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63275150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63276350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63277650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63278850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63280150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63281350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63282650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63283850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63285150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63286350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63287650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63288850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63290150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63291350.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63292650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 63293850.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63295150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63421402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63422650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63423902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63425150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63426402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63427650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63428902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63430150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63431402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63432650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63433902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63435150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63436402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63437650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63438902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63440150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63441402.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63442650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63443902.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63445150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63571480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63572650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63573980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63575150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63576480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63577650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63578980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63580150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63581480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63582650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63583980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63585150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63586480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63587650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63588980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63590150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63591480.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63592650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 63593980.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63595150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63722650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63725150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63727650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63730150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63732650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63735150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63737650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63740150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63742650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63745150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63872650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63875150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63877650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63880150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63882650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63885150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63887650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63890150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63892650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 63895150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64022650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64025150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64027650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64030150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64032650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64035150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64037650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64040150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64042650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64045150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64172650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64175150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64177650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64180150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64182650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64185150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64187650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64190150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64192650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64195150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64322650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64325150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64327650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64330150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64332650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64335150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64337650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64340150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64342650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64345150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64472650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64475150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64477650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64480150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64482650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64485150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64487650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64490150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64492650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64495150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64622650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64625150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64627650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64630150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64632650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64635150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64637650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64640150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64642650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64645150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64772650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64775150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64777650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64780150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64782650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64785150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64787650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64790150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64792650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64795150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64922650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64925150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64927650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64930150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64932650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64935150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64937650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64940150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64942650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 64945150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65072650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65075150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65077650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65080150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65082650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65085150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65087650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65090150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65092650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65095150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65222650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65225150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65227650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65230150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65232650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65235150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65237650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65240150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65242650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65245150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65372650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65375150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65377650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65380150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65382650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65385150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65387650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65390150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65392650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65395150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65522600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65522650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65525100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65525150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65527600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65527650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65530100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65530150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65532600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65532650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65535100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65535150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65537600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65537650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65540100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65540150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65542600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65542650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65545100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65545150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65672600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65672650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65675100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65675150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65677600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65677650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65680100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65680150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65682600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65682650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65685100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65685150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65687600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65687650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65690100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65690150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65692600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65692650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 65695100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65695150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65822650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65825150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65827650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65830150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65832650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65835150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65837650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65840150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65842650.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 65845150.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[22670000 ps] MRS -> -[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> -[10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> -[15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 66650 ns -Time Done: 90740 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 90820000.0 ps -[70000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 90840 ns -Time Done: 115330 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 115410000.0 ps -[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> -[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) -> -[10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> -[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 115430 ns -Time Done: 140000 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 140080000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> -[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> -[10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) -> -[17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> -[17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> -[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> -[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> -[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> -[10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> -[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> -[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> -[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> -[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> -[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> -[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> -[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> -[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> -[10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> -[17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> -[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> -[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> -[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> -[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> -[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> -[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> -[10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> -[10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> -[17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> -[10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> -[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> -[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> -[10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> -[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> -[10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> -[17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> -[17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) -> -[10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> -[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> -[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> -[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> -[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> -[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> -[10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> -[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> -[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> -[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> -[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> -[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> -[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> -[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> -[17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> -[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> -[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> -[10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> -[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> -[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> -[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> -[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> -[17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> -[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> -[10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> -[17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> -[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> -[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> -[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> -[17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> -[10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> -[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> -[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> -[10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> -[17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> -[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> -[10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> -[17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> -[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> -[10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> -[10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> -[10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> -[17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> -[17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> -[10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> -[17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> -[10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> -[17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> -[17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> -[10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> -[10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> -[10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> -[17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> -[17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> -[10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> -[17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> -[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> -[10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) -> -[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> -[10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> -[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> -[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> -[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> -[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> -[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> -[17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> -[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> -[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> -[10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> -[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> -[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> -[17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> -[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> -[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> -[10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> -[17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> -[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> -[10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> -[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> -[17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> -[10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> -[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> -[10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> -[17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> -[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> -[10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> -[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> -[17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> -[10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> -[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> -[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> -[10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> -[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> -[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> -[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> -[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> -[10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> -[17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> -[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> -[10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> -[10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> -[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> -[17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> -[17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> -[10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> -[17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> -[17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> -[10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> -[10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> -[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> -[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> -[10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> -[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> -[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> -[10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> -[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> -[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> -[17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> -[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> -[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> -[10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> -[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> -[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> -[17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> -[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> -[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> -[10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> -[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> -[10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> -[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> -[17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> -[10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> -[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> -[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> -[10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> -[17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> -[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> -[ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> -[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> -[ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) -> -[ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> -[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> -[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> -[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> -[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> -[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> -[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> -[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> -[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> -[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> -[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> -[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> -[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> -[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> -[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> -[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> -[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> -[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> -[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP -> -[40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> -[17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) -> -[17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> -[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> -[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> -[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> -[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> -[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> -[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> -[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> -[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> -[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> -[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> -[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> -[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> -[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> -[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> -[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> -[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> -[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> -[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> -[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> -[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> -[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> -[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) -> -[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> -[10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> -[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) -> -[ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> -[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) -> -[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> -[ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) -> -[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> -[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> -[10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> -[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> -[15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) -> -[10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> -[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> -[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> -[10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> -[15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> -[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) -> -[10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> -[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> -[15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> -[10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> -[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> -[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) -> -[10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> -[15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> -[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> -[10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> -[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> -[ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) -> -[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> -[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> -[ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> -[ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> -[15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> -[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> -[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> -[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> -[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> -[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> -[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> -[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> -[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> -[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> -[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> -[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> -[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> -[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> -[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> -[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> -[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> -[ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> -[10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> -[ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> -[10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> -[15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> -[15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> -[10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> -[15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> -[15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> -[10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) -> -[10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> -[10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> -[15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> -[15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) -> -[10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> -[15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> -[15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> -[10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> -[15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) -> -[ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) -> -[ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> -[10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> -[15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) -> -[10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> -[15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) -> -[10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> -[15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) -> -[10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) -> -[10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> -[15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) -> -[10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> -[15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> -[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> -[10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> -[ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> -[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> -[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> -[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> -[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> -[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> -[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> -[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> -[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> -[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> -[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> -[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> -[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> -[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> -[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> -[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> -[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) -> -[10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) -> -[15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> -[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> -[ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> -[10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> -[10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> -[10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> -[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> -[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> -[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> -[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> -[ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> -[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> -[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> -[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> -[ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> -[10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> -[10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> -[10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> -[10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> -[10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> -[10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> -[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> -[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 140100 ns -Time Done: 249710 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> -[10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 249840000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 250810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:16 ; elapsed = 00:47:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1332 ; free virtual = 24744 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2805770 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 14:58:39 2023... diff --git a/xsim/sim_busdelay10000_flybydelay3000.log b/xsim/sim_busdelay10000_flybydelay3000.log deleted file mode 100644 index cf630d4..0000000 --- a/xsim/sim_busdelay10000_flybydelay3000.log +++ /dev/null @@ -1,235 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 314324.0 ps WARNING: 200 us is required before RST_N goes inactive. -[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 825600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[370000 ps] MRS -> -[10000 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1198100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[220000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) -> [230000 ps] RD @ (0, 0) -> [220000 ps] RD @ (0, 0) -> \ No newline at end of file diff --git a/xsim/sim_busdelay1250_flybydelay600.log b/xsim/sim_busdelay1250_flybydelay600.log deleted file mode 100644 index d6d857a..0000000 --- a/xsim/sim_busdelay1250_flybydelay600.log +++ /dev/null @@ -1,11475 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 303174.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 814450.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> [370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1186950.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [560000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[327500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67813200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67815700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67818200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67820700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67823200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67825700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67828200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67830700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67833200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67835700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67963200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67965700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67968200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67970700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67973200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67975700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67978200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67980700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67983200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 67985700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 68135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68263276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68265776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68268276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68270776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68273276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68275776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68278276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68280776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68283276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68285776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68413354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68415854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68418354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68420854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68423354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68425854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68428354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68430854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68433354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68435854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70214450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70216950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70219450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70221950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70224450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70226950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70229450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70231950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70234450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70236950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70364450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70366950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70369450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70371950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70374450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70376950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70379450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70381950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70384450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70386950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70511950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 70534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71863200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71865700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71868200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71870700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71873200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71875700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71878200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71880700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71883200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 71885700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72013200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72015700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72018200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72020700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72023200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72025700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72028200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72030700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72033200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72035700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 72185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72313276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72315776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72318276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72320776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72323276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72325776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72328276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72330776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72333276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72335776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72463354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72465854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72468354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72470854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72473354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72475854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72478354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72480854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72483354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72485854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74264450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74266950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74269450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74271950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74274450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74276950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74279450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74281950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74284450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74286950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74414450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74416950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74419450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74421950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74424450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74426950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74429450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74431950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74434450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74436950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74561950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75913200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75915700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75918200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75920700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75923200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75925700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75928200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75930700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75933200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 75935700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76063200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76065700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76068200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76070700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76073200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76075700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76078200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76080700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76083200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76085700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76213200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76215700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76218200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76220700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76223200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76225700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76228200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76230700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76233200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76235700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76363276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76365776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76368276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76370776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76373276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76375776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76378276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76380776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76383276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76385776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76513354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76515854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76518354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76520854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76523354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76525854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76528354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76530854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76533354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76535854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78314450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78316950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78319450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78321950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78324450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78326950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78329450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78331950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78334450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78336950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78464450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78466950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78469450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78471950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78474450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78476950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78479450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78481950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78484450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78486950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78611950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78614450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78616950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78619450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78621950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78624450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78626950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78629450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78631950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 78634450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79963200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79965700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79968200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79970700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79973200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79975700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79978200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79980700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79983200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79985700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80263200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80265700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80268200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80270700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80273200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80275700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80278200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80280700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80283200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 80285700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80413276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80415776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80418276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80420776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80423276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80425776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80428276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80430776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80433276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80435776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80563354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80565854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80568354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80570854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80573354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80575854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80578354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80580854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80583354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80585854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82364450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82366950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82369450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82371950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82374450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82376950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82379450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82381950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82384450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82386950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82536950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82661950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82664450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82666950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82669450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82671950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82674450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82676950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82679450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82681950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 82684450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84013200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84015700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84018200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84020700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84023200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84025700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84028200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84030700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84033200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84035700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84313200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84315700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84318200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84320700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84323200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84325700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84328200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84330700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84333200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 84335700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84463276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84465776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84468276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84470776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84473276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84475776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84478276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84480776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84483276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84485776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84613354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84615854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84618354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84620854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84623354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84625854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84628354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84630854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84633354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84635854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86414450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86416950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86419450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86421950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86424450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86426950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86429450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86431950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86434450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86436950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86586950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86711950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86714450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86716950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86719450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86721950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86724450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86726950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86729450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86731950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 86734450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88063200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88065700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88068200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88070700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88073200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88075700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88078200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88080700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88083200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88085700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88213200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88215700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88218200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88220700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88223200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88225700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88228200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88230700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88233200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88235700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88363200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88365700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88368200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88370700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88373200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88375700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88378200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88380700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88383200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 88385700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88513276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88515776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88518276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88520776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88523276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88525776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88528276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88530776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88533276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88535776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88663354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88665854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88668354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88670854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88673354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88675854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88678354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88680854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88683354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88685854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 89884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90464450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90466950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90469450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90471950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90474450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90476950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90479450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90481950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90484450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90486950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90614450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90616950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90619450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90621950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90624450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90626950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90629450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90631950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90634450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90636950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90761950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90764450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90766950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90769450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90771950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90774450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90776950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90779450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90781950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90784450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 90934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92113200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92115700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92118200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92120700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92123200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92125700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92128200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92130700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92133200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92135700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92263200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92265700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92268200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92270700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92273200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92275700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92278200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92280700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92283200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92285700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92413200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92415700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92418200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92420700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92423200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92425700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92428200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92430700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92433200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 92435700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92563276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92565776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92568276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92570776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92573276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92575776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92578276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92580776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92583276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92585776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92713354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92715854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92718354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92720854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92723354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92725854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92728354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92730854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92733354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92735854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 93934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94514450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94516950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94519450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94521950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94524450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94526950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94529450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94531950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94534450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94536950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94664450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94666950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94669450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94671950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94674450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94676950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94679450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94681950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94684450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94686950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94811950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94814450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94816950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94819450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94821950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94824450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94826950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94829450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94831950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 94834450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 94984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 95884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96162028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96163200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96164528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96165700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96167028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96168200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96169528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96170700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96172028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96173200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96174528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96175700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96177028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96178200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96179528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96180700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96182028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96183200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96184528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96185700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96312028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96313200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96314528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96315700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96317028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96318200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96319528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96320700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96322028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96323200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96324528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96325700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96327028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96328200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96329528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96330700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96332028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96333200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96334528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96335700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96462028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96463200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96464528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96465700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96467028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96468200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96469528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96470700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96472028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96473200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96474528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96475700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96477028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96478200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96479528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96480700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96482028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96483200.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96484528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 96485700.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96612028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96613276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96614528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96615776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96617028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96618276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96619528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96620776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96622028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96623276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96624528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96625776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96627028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96628276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96629528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96630776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96632028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96633276.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96634528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96635776.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96762028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96763354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96764528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96765854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96767028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96768354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96769528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96770854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96772028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96773354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96774528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96775854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96777028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96778354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96779528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96780854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96782028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96783354.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96784528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 96785854.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96912028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96914528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96917028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96919528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96922028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96924528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96927028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96929528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96932028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 96934528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97062028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97064528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97067028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97069528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97072028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97074528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97077028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97079528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97082028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97084528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97212028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97214528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97217028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97219528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97222028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97224528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97227028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97229528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97232028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97234528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97362028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97364528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97367028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97369528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97372028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97374528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97377028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97379528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97382028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97384528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97512028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97514528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97517028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97519528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97522028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97524528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97527028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97529528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97532028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97534528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97662028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97664528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97667028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97669528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97672028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97674528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97677028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97679528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97682028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97684528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97812028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97814528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97817028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97819528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97822028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97824528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97827028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97829528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97832028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97834528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97962028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97964528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97967028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97969528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97972028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97974528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97977028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97979528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97982028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 97984528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98112028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98114528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98117028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98119528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98122028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98124528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98127028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98129528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98132028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98134528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98262028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98264528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98267028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98269528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98272028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98274528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98277028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98279528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98282028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98284528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98412028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98414528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98417028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98419528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98422028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98424528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98427028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98429528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98432028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98434528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98562028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98564450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98564528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98566950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98567028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98569450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98569528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98571950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98572028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98574450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98574528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98576950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98577028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98579450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98579528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98581950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98582028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98584450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98584528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98586950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98712028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98714450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98714528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98716950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98717028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98719450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98719528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98721950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98722028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98724450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98724528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98726950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98727028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98729450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98729528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98731950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98732028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98734450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98734528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98736950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98861950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98862028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98864450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98864528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98866950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98867028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98869450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98869528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98871950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98872028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98874450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98874528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98876950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98877028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98879450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98879528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98881950.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98882028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 98884450.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 98884528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99012028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99014528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99017028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99019528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99022028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99024528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99027028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99029528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99032028.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 99034528.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[32270000 ps] MRS -> -[10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> -[10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> -[15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 99840 ns -Time Done: 123930 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 124010000.0 ps -[70000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 124030 ns -Time Done: 148520 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 148600000.0 ps -[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> -[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) -> -[10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> -[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 148620 ns -Time Done: 173190 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 173270000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> -[10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> -[10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) -> -[17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> -[17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> -[10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> -[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> -[10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> -[10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> -[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> -[10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> -[10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> -[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> -[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> -[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> -[10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> -[17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> -[10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> -[17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> -[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> -[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> -[10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> -[17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> -[10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> -[17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> -[10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> -[10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> -[17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> -[10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> -[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> -[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> -[10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> -[17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> -[10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> -[17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> -[17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) -> -[10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> -[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> -[10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> -[10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> -[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> -[10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> -[10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> -[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> -[17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> -[10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> -[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> -[10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> -[17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> -[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> -[17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> -[10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> -[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> -[10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> -[17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> -[10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> -[17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> -[10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> -[17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> -[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> -[10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> -[17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> -[17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> -[10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> -[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> -[17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> -[10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> -[17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> -[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> -[10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> -[17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> -[17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> -[10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> -[17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> -[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> -[10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) -> -[42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> -[10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> -[10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> -[10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> -[10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> -[10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> -[17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> -[17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> -[10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> -[17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> -[17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> -[10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> -[10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> -[17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> -[17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> -[10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> -[17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> -[17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> -[10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> -[10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> -[17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> -[17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> -[10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> -[17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> -[17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> -[10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> -[17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> -[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> -[10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) -> -[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> -[10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> -[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> -[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> -[10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> -[17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> -[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> -[17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> -[10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> -[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> -[10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> -[17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> -[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> -[17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> -[10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> -[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> -[10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> -[17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> -[17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> -[10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> -[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> -[17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> -[10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> -[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> -[10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> -[17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> -[17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> -[10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> -[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> -[17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> -[10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> -[17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> -[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> -[10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> -[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> -[10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> -[17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> -[10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> -[17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> -[10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> -[17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> -[17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> -[10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> -[10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> -[10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> -[10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> -[10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> -[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> -[17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> -[10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> -[17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> -[17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> -[10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> -[17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> -[10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> -[17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> -[17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> -[10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> -[10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> -[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> -[10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> -[10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> -[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> -[10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> -[10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> -[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> -[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> -[17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> -[10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> -[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> -[10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> -[17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> -[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> -[17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> -[10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> -[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> -[10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> -[17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> -[10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> -[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> -[17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> -[10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> -[17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> -[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> -[10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> -[17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> -[17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> -[ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> -[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> -[ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) -> -[ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> -[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> -[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> -[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> -[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> -[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> -[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> -[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> -[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> -[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> -[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> -[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> -[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> -[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> -[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> -[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> -[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> -[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> -[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP -> -[40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> -[17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) -> -[17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> -[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> -[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> -[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> -[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> -[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> -[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> -[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> -[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> -[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> -[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> -[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> -[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> -[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> -[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> -[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> -[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> -[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> -[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> -[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> -[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> -[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> -[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) -> -[10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> -[10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> -[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) -> -[ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> -[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) -> -[ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> -[ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) -> -[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> -[ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> -[10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> -[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> -[15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) -> -[10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> -[15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> -[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> -[10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> -[15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> -[15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) -> -[10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> -[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> -[15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> -[10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> -[15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> -[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) -> -[10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> -[15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> -[15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> -[10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> -[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> -[ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) -> -[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> -[ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> -[ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> -[ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> -[15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> -[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> -[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> -[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> -[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> -[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> -[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> -[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> -[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> -[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> -[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> -[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> -[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> -[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> -[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> -[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> -[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> -[ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> -[ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> -[10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> -[ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> -[10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> -[15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> -[15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> -[10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> -[15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> -[15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> -[10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) -> -[10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> -[15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> -[15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> -[10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> -[15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> -[15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) -> -[10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> -[15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> -[15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> -[10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> -[15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) -> -[ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) -> -[ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) -> -[ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) -> -[ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> -[10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> -[15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) -> -[10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> -[15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> -[15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) -> -[10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> -[15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) -> -[10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> -[15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) -> -[10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> -[15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> -[15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) -> -[10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> -[15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> -[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> -[10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> -[ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> -[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> -[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> -[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> -[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> -[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> -[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> -[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> -[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> -[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> -[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> -[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> -[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> -[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> -[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> -[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> -[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) -> -[10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) -> -[15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> -[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> -[ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> -[10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> -[10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> -[10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> -[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> -[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> -[10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> -[ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> -[ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> -[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> -[10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> -[ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> -[ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> -[10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> -[10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> -[10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> -[10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> -[10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> -[10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> -[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> -[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 173290 ns -Time Done: 282900 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> -[10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 283030000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 284 us : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:17 ; elapsed = 00:53:20 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1238 ; free virtual = 24677 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147150 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 16:43:17 2023... diff --git a/xsim/sim_busdelay1875_flybydelay1000.log b/xsim/sim_busdelay1875_flybydelay1000.log deleted file mode 100644 index 56cb806..0000000 --- a/xsim/sim_busdelay1875_flybydelay1000.log +++ /dev/null @@ -1,12673 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 304199.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> [510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 815475.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1187975.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [580000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [347500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [110000 ps] NOP -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40324225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40326725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40329225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40331725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40334225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40336725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40339225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40341725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40344225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40346725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40474225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40476725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40479225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40481725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40484225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40486725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40489225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40491725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40494225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 40496725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40624291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40626791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40629291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40631791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40634291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40636791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40639291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40641791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40644291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40646791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40774369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40776869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40779369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40781869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40784369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40786869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40789369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40791869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40794369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40796869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42722975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42725475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42727975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42730475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42732975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42735475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42737975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42740475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42742975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42745475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42872975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42875475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42877975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42880475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42882975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42885475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42887975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42890475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42892975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 42895475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45124225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45126725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45129225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45131725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45134225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45136725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45139225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45141725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45144225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45146725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45274225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45276725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45279225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45281725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45284225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45286725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45289225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45291725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45294225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 45296725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45424291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45426791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45429291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45431791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45434291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45436791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45439291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45441791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45444291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45446791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45574369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45576869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45579369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45581869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45584369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45586869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45589369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45591869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45594369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45596869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47522975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47525475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47527975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47530475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47532975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47535475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47537975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47540475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47542975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47545475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47672975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47675475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47677975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47680475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47682975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47685475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47687975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47690475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47692975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 47695475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49924225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49926725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49929225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49931725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49934225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49936725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49939225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49941725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49944225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 49946725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50074225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50076725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50079225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50081725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50084225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50086725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50089225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50091725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50094225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 50096725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50224291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50226791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50229291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50231791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50234291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50236791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50239291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50241791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50244291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50246791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50374369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50376869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50379369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50381869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50384369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50386869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50389369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50391869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50394369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 50396869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 50995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 50995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 51895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 51895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52322975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52325475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52327975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52330475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52332975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52335475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52337975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52340475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52342975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52345475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52472975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52475475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52477975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52480475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52482975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52485475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52487975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52490475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52492975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 52495475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 52945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 53995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54724225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54726725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54729225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54731725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54734225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54736725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54739225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54741725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54744225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54746725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54874225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54876725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54879225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54881725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54884225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54886725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54889225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54891725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54894225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 54895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 54896725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55024291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55026791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55029291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55031791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55034291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55036791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55039291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55041791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55044291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55046791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55174369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55176869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55179369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55181869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55184369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55186869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55189369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55191869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55194369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 55196869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 55945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 56995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57122975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57125475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57127975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57130475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57132975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57135475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57137975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57140475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57142975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57145475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57272975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57275475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57277975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57280475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57282975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57285475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57287975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57290475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57292975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 57295475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 57895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 58945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59524225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59526725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59529225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59531725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59534225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59536725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59539225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59541725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59544225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59546725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59674225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59676725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59679225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59681725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59684225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59686725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59689225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59691725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59694225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 59696725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59824291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59826791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59829291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59831791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59834291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59836791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59839291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59841791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59844291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59846791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59974369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59976869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59979369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59981869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59984369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59986869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59989369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59991869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59994369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 59995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 59996869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 60895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61922975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61925475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61927975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61930475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61932975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61935475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61937975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61940475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61942975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 61945475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 61945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62072975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62075475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62077975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62080475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62082975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62085475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62087975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62090475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62092975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 62095475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 62995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 63895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64324225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64326725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64329225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64331725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64334225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64336725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64339225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64341725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64344225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64346725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64474225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64476725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64479225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64481725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64484225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64486725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64489225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64491725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64494225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 64496725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64624291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64626791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64629291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64631791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64634291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64636791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64639291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64641791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64644291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64646791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64774369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64776869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64779369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64781869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64784369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64786869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64789369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64791869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64794369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 64796869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 64945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 65995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66722975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66725475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66727975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66730475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66732975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66735475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66737975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66740475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66742975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66745475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66872975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66875475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66877975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66880475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66882975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66885475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66887975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66890475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66892975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 66895475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 66895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 67945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 68995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69124225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69126725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69129225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69131725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69134225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69136725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69139225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69141725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69144225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69146725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69274225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69276725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69279225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69281725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69284225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69286725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69289225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69291725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69294225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 69296725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69424291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69426791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69429291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69431791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69434291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69436791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69439291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69441791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69444291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69446791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69574369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69576869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69579369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69581869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69584369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69586869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69589369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69591869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69594369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 69596869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 69895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 70945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71522975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71525475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71527975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71530475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71532975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71535475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71537975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71540475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71542975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71545475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71672975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71675475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71677975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71680475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71682975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71685475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71687975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71690475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71692975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 71695475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 71995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 72895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73773043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73775543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73778043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73780543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73783043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73785543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73788043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73790543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73793043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73795543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73923043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73924225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73925543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73926725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73928043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73929225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73930543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73931725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73933043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73934225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73935543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73936725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73938043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73939225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73940543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73941725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73943043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73944225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 73945543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 73946725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74073043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74074225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74075543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74076725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74078043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74079225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74080543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74081725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74083043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74084225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74085543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74086725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74088043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74089225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74090543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74091725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74093043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74094225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74095543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 74096725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74223043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74224291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74225543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74226791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74228043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74229291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74230543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74231791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74233043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74234291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74235543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74236791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74238043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74239291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74240543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74241791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74243043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74244291.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74245543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74246791.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74373043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74374369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74375543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74376869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74378043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74379369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74380543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74381869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74383043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74384369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74385543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74386869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74388043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74389369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74390543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74391869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74393043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74394369.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74395543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 74396869.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74523043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74525543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74528043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74530543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74533043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74535543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74538043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74540543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74543043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74545543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74673043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74675543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74678043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74680543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74683043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74685543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74688043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74690543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74693043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74695543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74823043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74825543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74828043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74830543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74833043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74835543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74838043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74840543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74843043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74845543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74973043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74975543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74978043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74980543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74983043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74985543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74988043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74990543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74993043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 74995543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75123043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75125543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75128043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75130543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75133043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75135543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75138043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75140543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75143043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75145543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75273043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75275543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75278043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75280543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75283043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75285543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75288043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75290543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75293043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75295543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75423043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75425543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75428043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75430543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75433043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75435543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75438043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75440543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75443043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75445543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75573043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75575543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75578043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75580543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75583043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75585543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75588043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75590543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75593043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75595543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75723043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75725543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75728043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75730543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75733043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75735543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75738043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75740543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75743043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75745543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75873043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75875543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75878043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75880543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75883043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75885543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75888043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75890543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75893043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 75895543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76023043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76025543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76028043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76030543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76033043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76035543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76038043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76040543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76043043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76045543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76173043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76175543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76178043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76180543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76183043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76185543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76188043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76190543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76193043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76195543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76322975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76323043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76325475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76325543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76327975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76328043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76330475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76330543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76332975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76333043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76335475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76335543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76337975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76338043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76340475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76340543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76342975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76343043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76345475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76345543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76472975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76473043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76475475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76475543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76477975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76478043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76480475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76480543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76482975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76483043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76485475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76485543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76487975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76488043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76490475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76490543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76492975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76493043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 76495475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76495543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76623043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76625543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76628043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76630543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76633043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76635543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76638043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76640543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76643043.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 76645543.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[38270000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> [202500 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> -[10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> -[10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> -[10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> -[10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> -[10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> -[10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> -[10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> -[10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> -[10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> -[10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> -[10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> -[10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> -[10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> -[10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> -[10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> -[10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> -[10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> -[10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> -[10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> -[10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> -[10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> -[10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> -[10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> -[10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> -[ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> -[10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> -[10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> -[10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> -[10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> -[10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> -[10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> -[10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> -[10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> -[10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> -[10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> -[10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> -[10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> -[10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> -[10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> -[10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> -[10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> -[10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> -[10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> -[10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> -[10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> -[10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> -[10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> -[10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> -[10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> -[10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 0) -> -[ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> -[10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> -[10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> -[10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> -[10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> -[10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> -[10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> -[10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> -[10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> -[10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> -[10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> -[10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> -[10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> -[10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> -[10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> -[10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> -[10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> -[10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> -[10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> -[10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> -[10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> -[10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> -[10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> -[10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> -[10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> -[10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> [ 7500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> -[10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> -[10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> -[10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> -[10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> -[10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> -[10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> -[10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> -[10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> -[10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> -[10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> -[10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> -[10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> -[10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> -[10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> -[10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> -[10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> -[10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> -[10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> -[10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> -[10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> -[10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> -[10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> -[10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> -[10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> -[10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> -[10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> -[10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> -[10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> -[10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> -[10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> -[10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> -[10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> -[10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> -[10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> -[10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> -[10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> -[10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> -[10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> -[10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> -[10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> -[10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> -[10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> -[10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> -[10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> -[10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> -[10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> -[10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> -[10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> -[ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> -[10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> -[10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> -[10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> -[10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> -[10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> -[10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> -[10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> -[10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> -[10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> -[10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> -[10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> -[10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> -[10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> -[10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> -[10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> -[10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> -[10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> -[10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> -[10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> -[10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> -[10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> -[10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> -[10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> -[10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> -[10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> -[10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> -[ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> -[10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> -[10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> -[10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> -[10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> -[10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> -[10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> -[10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> -[10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> -[10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> -[10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> -[10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> -[10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> -[10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> -[10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> -[10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> -[10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> -[10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> -[10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> -[10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> -[10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> -[10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> -[10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> -[10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> -[10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> -[10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 1) -> -[ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> -[10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> -[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> -[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> -[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> -[10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> -[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> -[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> -[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> -[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> -[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> -[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> -[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> -[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> -[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> -[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> -[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> -[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> -[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> -[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> -[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> -[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> -[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> -[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> -[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> -[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> [ 7500 ps] WR @ (0, 976) -> -[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> -[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> -[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> -[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> -[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> -[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> -[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> -[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> -[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> -[ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> -[10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> -[10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> -[10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> -[10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> -[10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> -[10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> -[10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> -[10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> -[10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> -[10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> -[10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> -[10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> -[10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> -[10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> -[10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> -[10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> -[10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> -[10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> -[10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> -[10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> -[10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> -[10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> -[10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> -[10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 0) -> -[ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> -[10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> -[10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> -[10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> -[10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> -[10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> -[10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> -[10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> -[10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> -[10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> -[10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> -[10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> -[10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> -[10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> -[10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> -[10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> -[10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> -[10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> -[10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> -[10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> -[10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> -[10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> -[10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> -[10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> -[10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> [ 5000 ps] RD @ (2, 976) -> -[10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> -[10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> -[10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> -[10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> -[10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> -[10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> -[10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> -[10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> -[10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> -[10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> -[10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> -[10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> -[10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> -[10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> -[10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> -[10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> -[10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> -[10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> -[10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> -[10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> -[10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> -[10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> -[10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> -[10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> -[10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> -[10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> -[10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> -[10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> -[10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> -[10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> -[10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> -[10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> -[10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> -[10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> -[10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> -[10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> -[10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> -[10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> -[10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> -[10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> -[10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> -[10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> -[10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> -[10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> -[10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> -[10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> -[10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> -[10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> -[10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> -[10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> -[10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> -[10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> -[10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> -[10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> -[10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> -[10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> -[10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> -[10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> -[10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> -[10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> -[10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> -[10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> -[10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> -[10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> -[10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> -[ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> -[10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> -[10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> -[10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> -[10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> -[10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> -[10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> -[10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> -[10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> -[10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> -[10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> -[10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> -[10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> -[10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> -[10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> -[10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> -[10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> -[10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> -[10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> -[10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> -[10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> -[10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> -[10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> -[10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> -[10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> -[10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 0) -> -[ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> -[10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> -[10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> -[10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> -[10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> -[10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> -[10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> -[10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> -[10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> -[10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> -[10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> -[10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> -[10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> -[10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> -[10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> -[10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> -[10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> -[10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> -[10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> -[10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> -[10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> -[10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> -[10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> -[10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> -[10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> [ 5000 ps] RD @ (7, 976) -> -[10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> -[10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> - --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 77450 ns -Time Done: 101540 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [27500 ps] NOP -> -FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 101620000.0 ps -[70000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> -[10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> -[10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> -[10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> -[10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> -[10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> -[10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> -[10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> -[10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> -[10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> -[10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> -[10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> -[10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> -[10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> -[10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> -[10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> -[10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> -[10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> -[10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> -[10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> -[10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> -[10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> -[10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> -[10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> -[10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> -[ 2500 ps] ACT @ (2, 8192) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> -[10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> -[10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> -[10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> -[10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> -[10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> -[10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> -[10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> -[10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> -[10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> -[10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> -[10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> -[10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> -[10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> -[10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> -[10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> -[10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> -[10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> -[10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> -[10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> -[10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> -[10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> -[10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> -[10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> -[10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> -[10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> -[ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> -[10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> -[10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> -[10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> -[10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> -[10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> -[10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> -[10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> -[10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> -[10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> -[10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> -[10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> -[10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> -[10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> -[10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> -[10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> -[10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> -[10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> -[10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> -[10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> -[10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> -[10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> -[10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> -[10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> -[10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> -[10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> -[10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> -[10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> -[10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> -[10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> -[10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> -[10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> -[10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> -[10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> -[10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> -[10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> -[10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> -[10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> -[10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> -[10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> -[10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> -[10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> -[10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> -[10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> -[10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> -[10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> -[10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> -[10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> -[10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> -[10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> -[10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> -[10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> -[10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> -[10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> -[10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> -[10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> -[10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> -[10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> -[10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> -[10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> -[10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> -[10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> -[10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> -[10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> -[10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> -[10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> -[10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> -[10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> -[10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> -[10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> -[10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> -[10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> -[10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> -[10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> -[10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> -[10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> -[10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> -[10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> -[10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> -[10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 8192) -> -[17500 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> -[10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> -[10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> -[10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> -[10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> -[10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> -[10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> -[10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> -[10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> -[10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> -[10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> -[10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> -[10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> -[10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> -[10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> -[10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> -[10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> -[10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> -[10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> -[10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> -[10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> -[10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> -[ 2500 ps] ACT @ (7, 8192) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> -[10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> -[10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> -[10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> -[10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> -[10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> -[10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> -[10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> -[10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> -[10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> -[10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> -[10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> -[10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> -[10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> -[10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> -[10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> -[10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> -[10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> -[10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> -[10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> -[10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> -[10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> -[10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> -[10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> -[10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> -[10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> -[ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> -[10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> -[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> -[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> -[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> -[10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> -[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> -[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> -[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> -[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> -[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> -[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> -[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> -[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> -[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> -[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> -[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> -[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> -[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> -[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> -[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> -[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> -[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> -[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> -[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> -[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> -[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> -[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> -[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> -[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> -[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> -[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> -[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> -[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> -[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> -[ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> -[10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> -[10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> -[10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> -[10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> -[10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> -[10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> -[10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> -[10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> -[10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> -[10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> -[10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> -[10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> -[10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> -[10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> -[10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> -[10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> -[10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> -[10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> -[10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> -[10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> -[10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> -[10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> -[10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> -[10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> -[ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> -[10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> -[10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> -[10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> -[10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> -[10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> -[10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> -[10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> -[10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> -[10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> -[10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> -[10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> -[10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> -[10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> -[10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> -[10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> -[10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> -[10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> -[10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> -[10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> -[10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> -[10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> -[10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> -[10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> -[10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> -[10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> -[10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> -[10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> -[10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> -[10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> -[ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> -[10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> -[10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> -[10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> -[10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> -[10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> -[10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> -[10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> -[10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> -[10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> -[10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> -[10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> -[10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> -[10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> -[10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> -[10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> -[10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> -[10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> -[10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> -[10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> -[10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> -[10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> -[10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> -[10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> -[10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> -[10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> -[10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> -[10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> -[10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> -[10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> -[10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> -[10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> -[10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> -[10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> -[10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> -[10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> -[10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> -[10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> -[10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> -[10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> -[10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> -[10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> -[10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> -[10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> -[10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> -[10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> -[10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> -[10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> -[10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> -[10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> -[10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> -[10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> -[10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> -[10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> -[10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> -[10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> -[10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> -[10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> -[10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> -[10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> -[10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> -[10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> -[ 5000 ps] ACT @ (6, 8192) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> -[10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> -[10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> -[10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> -[10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> -[10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> -[10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> -[10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> -[10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> -[10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> -[10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> -[10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> -[10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> -[10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> -[10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> -[10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> -[10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> -[10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> -[10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> -[10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> -[10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> -[10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> -[10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> -[10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> -[10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> -[10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> -[ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> -[10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> -[10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> -[10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> -[10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> -[10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> -[10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> -[10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> -[10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> -[10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> -[10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> -[10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> -[10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> -[10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> -[10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> -[10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> -[10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> -[10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> -[10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> -[10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> -[10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> -[10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> -[10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> -[10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> -[10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> -[10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> -[10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> -[10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> - --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 101640 ns -Time Done: 126130 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 126210000.0 ps -[97500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> -[10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> -[10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> -[10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 16383) -> -[17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> -[10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> -[10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> -[10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> -[10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> -[10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> -[10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> -[10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> -[10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> -[10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> -[10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> -[10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> -[10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> -[10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> -[10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> -[10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> -[10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> -[10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> -[10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> -[10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> -[10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> -[10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> -[10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> -[10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> -[10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> -[10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> -[10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> -[10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> -[10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> -[10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> -[10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> -[10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> -[10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> -[10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> -[10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> -[10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> -[10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> -[10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> -[10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> -[10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> -[10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> -[10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> -[10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> -[10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> -[10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> -[10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> -[10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> -[10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> -[10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> -[10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> -[10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> -[10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> -[10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> -[10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> -[10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> -[10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> -[10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> -[10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> -[10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> -[10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> -[10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> -[10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> -[10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> -[10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> -[10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> -[10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> -[10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> -[10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> -[10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> -[10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> -[10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> -[10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> -[10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> -[10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> -[10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> -[10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> -[10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> -[10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> -[10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> -[10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> -[10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> -[10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> -[10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> -[10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> -[10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> -[10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> -[10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> -[10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> -[10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> -[10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> -[10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> -[10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> -[10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> -[10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> -[10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> -[10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> -[10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> -[10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> -[ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> -[10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> -[10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> -[10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> -[10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> -[10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> -[10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> -[10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> -[10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> -[10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> -[10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> -[10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> -[10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> -[10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> -[10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> -[10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> -[10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> -[10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> -[10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> -[10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> -[10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> -[10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> -[10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> -[10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> -[10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> -[10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> -[ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> -[10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> -[10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> -[10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> -[10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> -[10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> -[10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> -[10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> -[10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> -[10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> -[10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> -[10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> -[10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> -[10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> -[10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> -[10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> -[10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> -[10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> -[10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> -[10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> -[10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> -[10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> -[10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> -[10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> -[10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> -[10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> -[10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> -[10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> -[10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> -[10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> -[10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> -[10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> -[10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> -[10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> -[10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> -[10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> -[10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> -[10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> -[10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> -[10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> -[10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> -[10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> -[10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> -[10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> -[10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> -[10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> -[10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> -[10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> -[10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> -[10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> -[10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> -[10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> -[10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> -[10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> -[10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> -[10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> -[10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> -[10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> -[10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> -[10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> -[10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> -[10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> -[10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> -[10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> -[10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> -[10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> -[10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> -[10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> -[10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> -[10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> -[10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> -[10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> -[10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> -[10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> -[10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> -[10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> -[10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> -[10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> -[ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> -[10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> -[10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> -[10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> -[10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> -[10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> -[10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> -[10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> -[10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> -[10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> -[10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> -[10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> -[10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> -[10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> -[10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> -[10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> -[10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> -[10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> -[10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> -[10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> -[10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> -[10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> -[10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> -[10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> -[10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> -[10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> -[10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> -[10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> -[10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> -[10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> -[10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> -[10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> -[10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> -[10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> -[10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> -[10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> -[10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> -[10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> -[10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> -[10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> -[10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> -[10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> -[10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> -[10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> -[10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> -[10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> -[10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> -[10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> -[10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> -[10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> -[10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> -[ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> -[10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> -[10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> -[10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> -[10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> -[10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> -[10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> -[10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> -[10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> -[10000 ps] RD @ (3, 296) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> -[15000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> -[10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> -[10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> -[10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> -[10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> -[10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> -[10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> -[10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> -[10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> -[10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> -[10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> -[10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> -[10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> -[10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> -[10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> -[10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> -[10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> -[ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> -[10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> -[10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> -[10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> -[10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> -[10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> -[10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> -[10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> -[10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> -[10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> -[10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> -[10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> -[10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> -[10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> -[10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> -[10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> -[10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> -[10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> -[10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> -[10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> -[10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> -[10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> -[10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> -[10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> -[10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> -[10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> -[10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> -[10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> -[10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> -[10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> -[10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> -[10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> -[10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> -[10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> -[10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> -[10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> -[10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> -[10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> -[10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> -[10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> -[10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> -[10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> -[10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> -[10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> -[10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> -[10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> -[10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> -[10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> -[10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> -[10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> -[10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> -[10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> -[10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> -[10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> -[10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> -[10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> -[10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> -[10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> -[10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> -[10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> -[10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> -[10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> -[10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> -[10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> -[10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> -[10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> -[10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> -[10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> -[10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> -[10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> -[10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> -[10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> -[10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> -[10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> -[10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> -[10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> -[10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> -[10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> -[10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> -[10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> -[10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> -[10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> -[10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> -[10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> -[10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> -[10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> -[10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> -[10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> -[10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> -[10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> -[10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> -[10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> -[10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> -[10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> -[10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> -[10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> -[10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> -[10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> -[10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> -[ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> -[10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> -[10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> -[10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> -[10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> -[10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> -[10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> -[10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> -[10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> -[10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> -[10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> -[10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> -[10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> -[10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> -[10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> -[10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> -[ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 126230 ns -Time Done: 150800 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 150880000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> -[ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> -[10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> -[17500 ps] WR @ (4, 952) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> -[17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10602) -> -[10000 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> [17500 ps] WR @ (0, 944) -> -[ 2500 ps] ACT @ (4, 5206) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> -[10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> -[10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> -[10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> -[10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> -[10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> -[10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> -[10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> -[17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> -[10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> -[17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> -[10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> -[17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> -[10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> -[17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> -[10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> -[17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> -[10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> -[17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> -[10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> -[17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> -[10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> -[17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> -[17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> -[10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> -[17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> -[17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> -[10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> -[17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> -[17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> -[10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> -[17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> -[17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> -[10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> -[17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> -[17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> -[10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> -[17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> -[17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> -[10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> [17500 ps] WR @ (0, 784) -> -[ 2500 ps] ACT @ (4, 3928) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> -[10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> -[10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> -[10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> -[10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> -[10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> -[10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> -[17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> -[10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> -[17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> -[10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> -[17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> -[10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> -[17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> -[10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> -[17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> -[10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> -[17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> -[10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> -[17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> -[10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> -[17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> -[17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> -[10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> -[17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> -[17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> -[10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> -[17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> -[17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> -[10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> -[17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> -[17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> -[10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> -[17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> -[17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> -[10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> -[17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> -[17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> -[10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> [17500 ps] WR @ (0, 624) -> -[ 2500 ps] ACT @ (4, 2650) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> -[10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> -[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> -[10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> -[17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> -[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> -[17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> -[10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> -[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> -[10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> -[17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> -[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> -[17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> -[10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> -[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> -[10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> -[17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> -[17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> -[10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> -[17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> -[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> -[10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> -[17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> -[17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> -[10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> -[17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> -[17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> -[10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> -[17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> -[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> -[10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> -[17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> -[17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> -[10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> -[10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> -[10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> -[10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> [17500 ps] WR @ (0, 472) -> -[10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> -[ 7500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> -[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> -[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> -[10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> -[17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> -[10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> -[17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> -[17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> -[10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> -[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> -[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> -[10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> -[17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> -[17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> -[10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> -[17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> -[17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> -[10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> -[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> -[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> -[10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> -[17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> -[17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> -[10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> -[10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> -[10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> -[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> -[10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> -[10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> -[10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> -[10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> -[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> -[10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> -[17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [17500 ps] WR @ (0, 304) -> -[10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> [10000 ps] ACT @ (4, 5490) -> -[17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> -[17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 15399) -> -[42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> -[10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> -[10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> -[10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> -[10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> -[10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> -[10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> -[10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> -[17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> -[10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> -[17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> -[10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> -[17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> -[10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> -[17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> -[10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> -[17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> -[10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> -[17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> -[10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> -[17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> -[10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> -[17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> -[17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> -[10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> -[17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> -[17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> -[10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> -[17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> -[17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> -[10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> -[17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> -[17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> -[10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> -[17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> -[17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> -[10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> -[17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> -[17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> -[10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> [ 2500 ps] ACT @ (0, 14121) -> -[42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> -[10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> -[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> -[10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> -[10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> -[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> -[10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> -[10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> -[17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> -[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> -[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> -[10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> -[17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> -[10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> -[17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> -[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> -[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> -[10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> -[17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> -[10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> -[17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> -[10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> -[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> -[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> -[10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> -[17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> -[17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> -[10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> -[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> -[17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> -[10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> -[17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> -[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> -[10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> -[17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> -[17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> -[10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> -[17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> -[17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> -[10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> -[17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> -[15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> -[17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> -[ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> -[17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> -[ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> -[ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 7500 ps] WR @ (7, 1008) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> [17500 ps] WR @ (7, 1008) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> -[17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> [10000 ps] ACT @ (0, 16081) -> -[ 7500 ps] WR @ (3, 1008) -> [ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 11764) -> [10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> -[17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5484) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 88) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> -[10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> -[17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> -[10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> -[17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> -[10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> -[17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> -[10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> -[17500 ps] WR @ (3, 952) -> [10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> -[10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> -[17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> -[10000 ps] WR @ (3, 944) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> -[17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> -[10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> -[17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> -[10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> -[17500 ps] WR @ (3, 936) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> -[17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> -[10000 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> -[17500 ps] WR @ (3, 928) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> -[17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> -[10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> -[17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> -[17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> -[10000 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> -[17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> -[17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> -[10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> -[17500 ps] WR @ (3, 912) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> -[17500 ps] WR @ (3, 912) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> -[10000 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> -[17500 ps] WR @ (3, 904) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> -[17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> -[10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 3226) -> [10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8818) -> [10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 14410) -> [10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> -[ 5000 ps] NOP -> [40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (7, 3814) -> [17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2735) -> -[17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> -[10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> -[17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> -[10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> -[17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> -[10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> -[17500 ps] WR @ (7, 832) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> -[17500 ps] WR @ (7, 832) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> -[10000 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> -[17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> -[17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> -[10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> -[17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> -[17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> -[10000 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> -[17500 ps] WR @ (7, 816) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> -[17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> -[10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> -[17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> -[17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> -[10000 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> -[17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> -[17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> -[10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 14311) -> [10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3519) -> [10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 9111) -> [10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> -[35000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> -[10000 ps] ACT @ (0, 694) -> [15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> -[15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> -[15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> -[10000 ps] ACT @ (4, 10602) -> [ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> -[15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> -[15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> -[10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> -[15000 ps] RD @ (4, 944) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> -[15000 ps] RD @ (4, 944) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> -[10000 ps] ACT @ (4, 16194) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> -[15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> -[15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> -[10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> -[15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> -[15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> -[10000 ps] ACT @ (4, 5402) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> -[15000 ps] RD @ (4, 928) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> -[15000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> -[10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9915) -> [10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6678) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15507) -> [10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12270) -> [15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4715) -> [10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1478) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [15000 ps] RD @ (4, 856) -> -[10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7461) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 848) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> [ 5000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> [10000 ps] RD @ (4, 848) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> -[ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> -[ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> -[10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> -[10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> -[15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> -[10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> -[10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> -[10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> -[15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> -[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> -[10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> -[10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> -[15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> -[ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> -[ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> -[10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> -[10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> -[10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> -[15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> -[15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> -[10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> -[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> -[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12363) -> -[10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> -[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> -[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6967) -> -[10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> [15000 ps] RD @ (4, 624) -> -[ 5000 ps] ACT @ (0, 492) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> [ 5000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11480) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> -[10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 688) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6280) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> -[15000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> -[ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> -[ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> -[10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> -[ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> -[ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> -[ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> -[ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> -[10000 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> -[15000 ps] RD @ (4, 552) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> -[15000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> -[10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> -[15000 ps] RD @ (4, 544) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> -[15000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> -[10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> -[15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> -[15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> -[10000 ps] ACT @ (4, 11380) -> [ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> -[15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> -[15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> -[10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> -[15000 ps] RD @ (4, 528) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> -[15000 ps] RD @ (4, 528) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> -[10000 ps] ACT @ (4, 588) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> -[15000 ps] RD @ (4, 520) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> -[15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> -[10000 ps] ACT @ (4, 11576) -> [ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5101) -> [10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 16089) -> [10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12852) -> [15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10693) -> [10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8535) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5297) -> [10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3139) -> [15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2060) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 16285) -> [10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14127) -> [15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13048) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10889) -> [10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2647) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (0, 448) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> -[10000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8239) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13831) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> -[10000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> -[10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> -[15000 ps] RD @ (0, 416) -> [10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> -[10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> -[ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [15000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> [10000 ps] ACT @ (4, 9710) -> -[ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [15000 ps] RD @ (4, 408) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [15000 ps] RD @ (4, 400) -> -[10000 ps] RD @ (0, 400) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5394) -> -[10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> -[15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> -[10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> -[15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> -[10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> -[15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> -[10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> -[15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> -[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> -[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> -[ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> -[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> -[10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> -[15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> -[10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> -[15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> -[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> -[10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> -[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> -[15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> -[10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> -[15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> -[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (4, 184) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> -[10000 ps] RD @ (0, 176) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7058) -> -[15000 ps] RD @ (0, 176) -> [ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> -[ 5000 ps] RD @ (4, 176) -> [10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> -[10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> -[ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> -[ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (4, 160) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> -[ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> -[ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> -[ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> -[10000 ps] ACT @ (0, 7450) -> [15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> -[15000 ps] RD @ (4, 144) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> -[15000 ps] RD @ (4, 144) -> [10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> -[10000 ps] ACT @ (4, 974) -> [ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> -[15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> -[15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> -[10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> -[15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> -[15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> -[10000 ps] ACT @ (4, 6566) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> -[15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> -[15000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> -[10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> -[15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> -[15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> -[10000 ps] ACT @ (4, 12158) -> [ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> -[15000 ps] RD @ (4, 120) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> -[15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> -[10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 287) -> [10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13434) -> [15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5879) -> [10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2642) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11471) -> [10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8234) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14217) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> -[10000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3425) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> -[10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9017) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> -[10000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> -[10000 ps] RD @ (0, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> -[15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> -[ 5000 ps] RD @ (0, 8) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> -[10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> -[ 5000 ps] RD @ (0, 0) -> [10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> -[10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> -[15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> -[15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> -[15000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10489) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 4013) -> [10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 1855) -> [10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 12843) -> [10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (3, 7447) -> [10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> -[15000 ps] RD @ (7, 992) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 3130) -> -[10000 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> -[10000 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> -[15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> [ 5000 ps] ACT @ (0, 10881) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> -[15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> -[10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> -[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> -[15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> -[10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> -[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> -[10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> -[ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> -[ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> -[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> -[10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> -[ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> -[ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> -[10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> -[15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> -[15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> -[10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> -[15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> -[15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> -[10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> -[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> -[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> -[10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> -[15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> -[15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> -[10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> -[15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> -[15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> -[10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> -[15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> -[15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> -[10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> -[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> -[10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> -[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> -[10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> -[15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> -[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> -[10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> -[ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> -[ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> -[ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> -[10000 ps] RD @ (7, 776) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (7, 10190) -> -[10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 150900 ns -Time Done: 260510 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> -[15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> -[15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 260640000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 261610 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:17 ; elapsed = 00:57:38 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 174 ; free virtual = 23702 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2965430 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 17:44:52 2023... diff --git a/xsim/sim_busdelay2500_flybydelay1500.log b/xsim/sim_busdelay2500_flybydelay1500.log deleted file mode 100644 index 6b8012e..0000000 --- a/xsim/sim_busdelay2500_flybydelay1500.log +++ /dev/null @@ -1,5129 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 305324.0 ps WARNING: 200 us is required before RST_N goes inactive. -[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 816600.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1189100.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[660000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [660000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [160000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [140000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> -[150000 ps] RD @ (0, 0) -> [150000 ps] RD @ (0, 0) -> [427500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> -[110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86234100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86236600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86239100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86241600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86244100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86246600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86249100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86251600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86254100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86256600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86384100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86386600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86389100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86391600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86394100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86396600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86399100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86401600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86404100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 86406600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86984136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86986636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86989136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86991636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86994136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86996636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86999136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87001636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87004136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87006636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87134100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87136600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87139100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87141600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87144100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87146600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87149100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87151600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87154100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87156600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87284100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87286600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87289100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87291600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87294100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87296600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87299100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87301600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87304100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 87306600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88034100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88036600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88039100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88041600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88044100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88046600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88049100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88051600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88054100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88056600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88184100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88186600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88189100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88191600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88194100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88196600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88199100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88201600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88204100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 88206600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88934100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88936600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88939100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88941600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88944100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88946600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88949100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88951600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88954100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 88956600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89084100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89086600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89089100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89091600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89094100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89096600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89099100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89101600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89104100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 89106600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89834100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89836600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89839100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89841600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89844100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89846600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89849100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89851600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89854100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89856600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89984100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89984136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89984136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89984136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89984136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89986600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89986636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89986636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89986636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89986636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89989100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89989136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89989136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89989136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89989136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89991600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89991636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89991636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89991636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89991636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89994100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89994136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89994136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89994136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89994136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89996600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89996636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89996636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89996636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89996636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 89999100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 89999136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 89999136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 89999136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 89999136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 90001600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90001636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90001636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90001636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90001636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 90004100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90004136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90004136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90004136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90004136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 90006600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90006636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90006636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90006636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90006636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90134136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90136636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90139136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90141636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90144136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90146636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90149136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90151636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90154136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90156636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90284136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90286636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90289136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90291636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90294136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90296636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90299136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90301636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90304136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90306636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90434136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90436636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90439136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90441636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90444136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90446636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90449136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90451636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90454136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90456636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90584136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90586636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90589136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90591636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90594136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90596636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90599136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90601636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90604136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90606636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90734100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90734136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90736600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90736636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90739100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90739136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90741600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90741636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90744100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90744136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90746600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90746636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90749100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90749136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90751600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90751636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90754100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90754136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90756600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90756636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90884100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90884136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90886600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90886636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90889100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90889136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90891600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90891636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90894100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90894136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90896600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90896636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90899100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90899136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90901600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90901636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90904100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90904136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 90906600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 90906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 90906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 90906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 90906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 90906636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91034136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91036636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91039136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91041636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91044136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91046636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91049136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91051636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91054136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91056636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91184136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91186636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91189136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91191636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91194136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91196636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91199136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91201636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91204136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91206636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91334136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91336636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91339136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91341636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91344136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91346636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91349136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91351636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91354136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91356636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91484136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91486636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91489136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91491636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91494136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91496636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91499136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91501636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91504136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91506636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91634100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91634136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91636600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91636636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91639100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91639136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91641600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91641636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91644100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91644136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91646600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91646636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91649100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91649136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91651600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91651636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91654100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91654136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91656600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91656636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91784100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91784136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91786600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91786636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91789100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91789136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91791600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91791636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91794100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91794136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91796600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91796636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91799100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91799136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91801600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91801636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91804100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91804136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 91806600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91806636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91934136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91936636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91939136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91941636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91944136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91946636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91949136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91951636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91954136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 91956636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92084136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92086636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92089136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92091636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92094136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92096636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92099136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92101636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92104136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92106636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92234136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92236636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92239136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92241636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92244136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92246636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92249136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92251636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92254136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92256636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92384136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92386636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92389136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92391636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92394136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92396636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92399136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92401636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92404136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92406636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92534100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92534136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92536600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92536636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92539100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92539136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92541600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92541636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92544100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92544136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92546600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92546636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92549100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92549136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92551600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92551636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92554100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92554136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92556600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92556636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92684100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92684136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92686600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92686636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92689100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92689136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92691600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92691636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92694100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92694136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92696600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92696636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92699100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92699136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92701600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92701636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92704100.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92704136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 92706600.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92706636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92834136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92836636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92839136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92841636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92844136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92846636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92849136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92851636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92854136.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 92856636.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[7070000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> -[372500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> -[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> -[10000 ps] RD @ (2, 816) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> -[15000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 93830 ns -Time Done: 118400 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 118490000.0 ps -[107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 5000 ps] PRE @ (1) -> -[ 5000 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 8192) -> [17500 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (2, 8192) -> [10000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 118500 ns -Time Done: 142600 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [47500 ps] NOP -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 142690000.0 ps -[70000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 142700 ns -Time Done: 167210 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 167300000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> -[45000 ps] PRE @ (4) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 12761) -> [17500 ps] WR @ (0, 952) -> [ 2500 ps] ACT @ (4, 10602) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11682) -> -[17500 ps] WR @ (0, 952) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> -[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5206) -> [10000 ps] ACT @ (0, 6286) -> -[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> -[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> -[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> -[10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> -[17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> -[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> -[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> -[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> -[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> -[10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> -[10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> -[10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> -[10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> -[10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> -[10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> -[10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> -[10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> -[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> -[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> -[10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> -[10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 11483) -> [17500 ps] WR @ (0, 792) -> [ 2500 ps] ACT @ (4, 9324) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10404) -> -[17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> -[10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> -[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> -[17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> -[10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> -[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> -[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> -[10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> -[17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> -[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> -[10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> -[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> -[17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> -[10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> -[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> -[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> -[10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> -[17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> -[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> -[10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> -[10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> -[10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> -[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> -[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> -[10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> -[10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> -[10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> -[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> -[10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> -[17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> -[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> -[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> -[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> -[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> -[10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> -[17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 2500 ps] ACT @ (4, 8046) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> -[17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> -[10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> -[17500 ps] WR @ (0, 624) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> -[17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> -[10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> -[10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> -[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> -[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> -[10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> -[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> -[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> -[10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> -[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> -[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> -[17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> -[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> -[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> -[10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> -[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> -[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> -[17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> -[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> -[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> -[10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> -[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> -[10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> -[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> -[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> -[10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> -[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> -[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> -[10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> -[17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> -[17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 7500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2451) -> [10000 ps] ACT @ (0, 3531) -> [17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> -[10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> -[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> -[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> -[10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> -[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> -[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> -[10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> -[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> -[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> -[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> -[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> -[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> -[10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> -[17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> -[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> -[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> -[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> -[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> -[10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> -[17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> -[10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> -[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> -[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> -[10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> -[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> -[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> -[10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> -[17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> -[17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> -[10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> -[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> -[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> -[10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> -[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> -[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> -[10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> -[17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> -[17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> -[10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [35000 ps] NOP -> -[10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> -[17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 6569) -> -[17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 4411) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15399) -> [10000 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> -[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> -[10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> -[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> -[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> -[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> -[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> -[10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> -[17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> -[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> -[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> -[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> -[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> -[10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> -[17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> -[10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> -[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> -[10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> -[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> -[10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> -[17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> -[10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> -[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> -[10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> -[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> -[10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> -[17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> -[10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> -[17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> -[10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> -[10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 5291) -> -[17500 ps] WR @ (4, 144) -> [ 2500 ps] ACT @ (0, 3133) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> -[10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> -[17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> -[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> -[17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> -[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> -[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> -[10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> -[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> -[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> -[17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> -[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> -[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> -[10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> -[10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> -[10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> -[10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> -[10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> -[10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> -[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> -[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> -[10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> -[ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5093) -> [10000 ps] ACT @ (7, 5092) -> -[17500 ps] WR @ (7, 1008) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2935) -> [12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4013) -> -[17500 ps] WR @ (7, 1008) -> [ 2500 ps] ACT @ (4, 1855) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> -[ 2500 ps] ACT @ (3, 1855) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 7500 ps] WR @ (7, 1000) -> [ 2500 ps] ACT @ (4, 13922) -> [42500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> -[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> -[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> -[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> -[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> -[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> -[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> -[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> -[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> -[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> -[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> -[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> -[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> -[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> -[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> -[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> -[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> -[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> -[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [12500 ps] NOP -> [ 5000 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 10290) -> [10000 ps] ACT @ (7, 9210) -> [ 7500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3814) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1656) -> [10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> -[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> -[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> -[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> -[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> -[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> -[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> -[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> -[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> -[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> -[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> -[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> -[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> -[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> -[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> -[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> -[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> -[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> -[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> -[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> -[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> -[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> -[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [ 2500 ps] NOP -> [12500 ps] RD @ (4, 856) -> -[10000 ps] RD @ (0, 856) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9620) -> -[15000 ps] RD @ (0, 856) -> [ 5000 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> -[ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> -[ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> -[10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> -[10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> -[15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> -[10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> -[10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> -[10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> -[15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> -[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> -[10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> -[10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> -[15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> -[ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> -[ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> -[10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> -[10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> -[10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> -[15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> -[15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> -[10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> -[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> -[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1571) -> [10000 ps] ACT @ (0, 492) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [15000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> -[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> -[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> -[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> -[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> -[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> -[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> -[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> -[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> -[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> -[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> -[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> -[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> -[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> -[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> -[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> -[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> -[ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 5000 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> -[15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> -[10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5394) -> -[10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> -[15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> -[10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> -[15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> -[10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> -[15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> -[10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> -[15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> -[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> -[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> -[ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> -[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> -[10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> -[15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> -[10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> -[15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> -[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> -[10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> -[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> -[15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> -[10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> -[15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> -[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [10000 ps] RD @ (4, 184) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> -[10000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4899) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> -[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> -[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> -[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> -[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> -[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> -[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> -[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> -[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> -[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> -[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> -[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> -[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> -[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> -[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> -[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> -[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (0, 10685) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10684) -> -[15000 ps] RD @ (7, 1000) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9606) -> -[10000 ps] ACT @ (7, 9605) -> [10000 ps] ACT @ (4, 8526) -> [ 5000 ps] RD @ (7, 1000) -> [ 5000 ps] ACT @ (3, 8526) -> [15000 ps] RD @ (3, 1000) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> -[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 5000 ps] RD @ (3, 992) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 2051) -> [10000 ps] ACT @ (4, 972) -> [ 5000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 5000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> -[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> -[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> -[10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> -[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> -[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> -[10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> -[10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> -[15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> -[ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> -[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> -[ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> -[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> -[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> -[10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> -[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> -[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> -[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> -[10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> -[15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> -[15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> -[10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> -[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> -[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> -[10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> -[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> -[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> -[10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> -[15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> -[15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> -[10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> -[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> -[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> -[10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> -[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> -[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> -[10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 5000 ps] ACT @ (7, 281) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> -[27500 ps] PRE @ (3) -> --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 167310 ns -Time Done: 276870 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 277010000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 277970 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:18 ; elapsed = 00:59:53 . Memory (MB): peak = 2833.148 ; gain = 476.559 ; free physical = 1580 ; free virtual = 24408 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3147790 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 18:48:36 2023... diff --git a/xsim/sim_busdelay5000_flybydelay2200.log b/xsim/sim_busdelay5000_flybydelay2200.log deleted file mode 100644 index d44aab7..0000000 --- a/xsim/sim_busdelay5000_flybydelay2200.log +++ /dev/null @@ -1,7620 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> [195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 308524.0 ps WARNING: 200 us is required before RST_N goes inactive. -[510000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 819800.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1192300.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [460000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[170000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [180000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> -[190000 ps] RD @ (0, 0) -> [190000 ps] RD @ (0, 0) -> [227500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> -[110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72197300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72199800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72202300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72204800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72207300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72209800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72212300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72214800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72217300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72219800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72347300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72349800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72352300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72354800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72357300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72359800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72362300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72364800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72367300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 72369800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 72969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 73999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74447300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74449800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74452300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74454800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74457300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74459800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74462300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74464800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74467300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74469800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74597300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74599800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74602300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74604800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74607300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74609800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74612300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74614800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74617300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 74619800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 74919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 74919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 75969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 75969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76697300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76699800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76702300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76704800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76707300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76709800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76712300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76714800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76717300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76719800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76847300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76849800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76852300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76854800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76857300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76859800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76862300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76864800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76867300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 76869800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 76999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 77919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78947300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78949800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78952300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78954800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78957300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78959800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78962300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78964800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78967300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 78969800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 78969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79097300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79099800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79102300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79104800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79107300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79109800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79112300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79114800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79117300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 79119800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 79999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 80919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81197300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81199800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81202300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81204800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81207300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81209800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81212300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81214800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81217300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81219800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81347300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81349800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81352300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81354800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81357300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81359800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81362300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81364800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81367300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 81369800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 81969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 82999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83447300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83449800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83452300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83454800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83457300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83459800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83462300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83464800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83467300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83469800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83597300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83599800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83602300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83604800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83607300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83609800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83612300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83614800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83617300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 83619800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 83919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 84969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85397338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85399838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85402338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85404838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85407338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85409838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85412338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85414838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85417338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85419838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85547338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85549838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85552338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85554838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85557338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85559838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85562338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85564838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85567338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85569838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85697300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85697338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85699800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85699838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85702300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85702338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85704800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85704838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85707300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85707338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85709800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85709838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85712300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85712338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85714800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85714838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85717300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85717338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85719800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85719838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85847300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85847338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85849800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85849838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85852300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85852338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85854800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85854838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85857300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85857338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85859800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85859838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85862300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85862338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85864800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85864838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85867300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85867338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 85869800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85869838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 85997338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 85999838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86002338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86004838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86007338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86009838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86012338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86014838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86017338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86019838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86147338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86149838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86152338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86154838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86157338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86159838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86162338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86164838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86167338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86169838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86297338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86299838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86302338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86304838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86307338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86309838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86312338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86314838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86317338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86319838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86447338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86449838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86452338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86454838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86457338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86459838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86462338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86464838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86467338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86469838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86597338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86599838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86602338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86604838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86607338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86609838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86612338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86614838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86617338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86619838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86747338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86749838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86752338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86754838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86757338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86759838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86762338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86764838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86767338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86769838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86897338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86899838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86902338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86904838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86907338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86909838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86912338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86914838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86917338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 86919838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87047338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87049838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87052338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87054838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87057338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87059838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87062338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87064838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87067338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87069838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87197338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87199838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87202338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87204838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87207338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87209838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87212338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87214838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87217338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87219838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87347338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87349838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87352338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87354838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87357338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87359838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87362338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87364838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87367338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87369838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87497338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87499838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87502338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87504838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87507338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87509838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87512338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87514838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87517338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87519838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87647338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87649838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87652338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87654838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87657338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87659838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87662338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87664838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87667338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87669838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87797338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87799838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87802338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87804838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87807338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87809838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87812338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87814838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87817338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87819838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87947300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87947338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87949800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87949838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87952300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87952338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87954800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87954838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87957300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87957338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87959800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87959838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87962300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87962338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87964800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87964838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87967300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87967338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 87969800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 87969838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88097300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88097338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88099800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88099838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88102300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88102338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88104800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88104838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88107300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88107338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88109800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88109838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88112300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88112338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88114800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88114838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88117300.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88117338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 88119800.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88119838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88247338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88249838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88252338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88254838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88257338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88259838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88262338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88264838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88267338.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 88269838.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[17870000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> -[372500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [ 5000 ps] NOP -> -[ 5000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> -[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> -[10000 ps] RD @ (2, 816) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> -[15000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 89240 ns -Time Done: 113810 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 113900000.0 ps -[107500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 5000 ps] PRE @ (1) -> -[ 5000 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 8192) -> [17500 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (2, 8192) -> [10000 ps] ACT @ (3, 8192) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> -[10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 113910 ns -Time Done: 138010 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [47500 ps] NOP -> FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 138100000.0 ps -[70000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> -[10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> -[10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> -[10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> -[10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> -[10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> -[10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> -[10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> -[10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> -[10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> -[10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> -[10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> -[10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> -[10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> -[10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> -[10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> -[10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> -[10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> -[10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> -[10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> -[10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> -[10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> -[10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> -[10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> -[ 2500 ps] ACT @ (1, 16383) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> -[10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> -[10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> -[10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> -[10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> -[10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> -[10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> -[10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> -[10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> -[10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> -[10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> -[10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> -[10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> -[10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> -[10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> -[10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> -[10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> -[10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> -[10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> -[10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> -[10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> -[10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> -[10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> -[10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> -[10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> -[10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> -[ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> -[10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> -[10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> -[10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> -[10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> -[10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> -[10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> -[10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> -[10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> -[10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> -[10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> -[10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> -[10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> -[10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> -[10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> -[10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> -[10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> -[10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> -[10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> -[10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> -[10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> -[10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> -[10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> -[10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> -[10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> -[10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> -[10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> -[10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> -[10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> -[10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> -[10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> -[10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> -[10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> -[10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> -[10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> -[10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> -[10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> -[10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> -[10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> -[10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> -[10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> -[10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> -[10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> -[10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> -[10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> -[10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> -[10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> -[10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> -[10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> -[10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> -[10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> -[10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> -[10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> -[10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> -[10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> -[10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> -[10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> -[10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> -[10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> -[10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> -[10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> -[10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> -[10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> -[10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> -[10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> -[10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> -[10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> -[10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> -[10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> -[10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> -[10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> -[10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> -[10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> -[10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> -[10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> -[10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> -[10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> -[10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> -[10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> -[10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> -[10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> -[10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> -[10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> -[10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> -[10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> -[10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> -[10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> -[10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> -[10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> -[10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> -[10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> -[10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> -[10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> -[10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> -[10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> -[10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> -[10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> -[10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> -[10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> -[10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> -[10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> -[10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> -[10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> -[ 2500 ps] ACT @ (6, 16383) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> -[10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> -[10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> -[10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 96) -> -[10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> -[10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> -[10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> -[10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> -[10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> -[10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> -[10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> -[10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> -[10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> -[10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> -[10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> -[10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> -[10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> -[10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> -[10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> -[10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> -[10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> -[10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> -[10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> -[10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> -[10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> -[10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> -[ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> -[10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> -[10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> -[10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> -[10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> -[10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> -[10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> -[10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> -[10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> -[10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> -[10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> -[10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> -[10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> -[10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> -[10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> -[10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> -[10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> -[10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> -[10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> -[10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> -[10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> -[10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> -[10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> -[10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> -[10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> -[10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> -[10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> -[10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16383) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> -[10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> -[10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> -[10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> -[10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> -[10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> -[10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> -[10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> -[10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> -[10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> -[10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> -[10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> -[10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> -[10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> -[10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> -[10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> -[10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> -[10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> -[10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> -[10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> -[10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> -[10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> -[10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> -[10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> -[10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> -[10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> -[10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> -[10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> -[10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> -[10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> -[10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> -[10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> -[10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> -[10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> -[10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> -[10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> -[10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> -[10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> -[10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> -[10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> -[10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> -[10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> -[10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> -[10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> -[10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> -[10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> -[10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> -[10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> -[10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> -[10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> -[10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> -[10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> -[10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> -[10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> -[10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> -[10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> -[10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> -[10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> -[10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> -[10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> -[10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> -[10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> -[10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> -[10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> -[10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> -[10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> -[10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> -[10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> -[10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> -[10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> -[10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> -[10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> -[10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> -[10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> -[10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> -[10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> -[10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> -[10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> -[10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> -[10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> -[10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> -[10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> -[10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> -[10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> -[10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> -[10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> -[10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> -[10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> -[10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> -[10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> -[10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> -[ 5000 ps] ACT @ (5, 16383) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> -[10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> -[10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> -[10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> -[10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> -[10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> -[10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> -[10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> -[10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> -[10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> -[10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> -[10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> -[10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> -[10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> -[10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> -[10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> -[10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> -[10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> -[10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> -[10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> -[10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> -[10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> -[10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> -[10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> -[10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> -[10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> -[ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> -[10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> -[10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> -[10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> -[10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> -[10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> -[10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> -[10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> -[10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> -[10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> -[10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> -[10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> -[10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> -[10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> -[10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> -[10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> -[10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> -[10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> -[10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> -[10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> -[10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> -[10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> -[10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> -[10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> -[10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> -[10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> -[10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> -[10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> -[10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> -[10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> -[10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> -[10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> -[10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> -[10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> -[10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> -[10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> -[10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> -[10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> -[10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> -[10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> -[10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> -[10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> -[10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> -[10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> -[10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> -[10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> -[10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> -[10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> -[10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> -[10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> -[10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> -[10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> -[10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> -[10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> -[10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> -[10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> -[10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> -[10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> -[10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> -[10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> -[10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> -[10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> -[10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> -[10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> -[10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> -[10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> -[10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> -[10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 138110 ns -Time Done: 162620 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 162710000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2852) -> [10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> -[45000 ps] PRE @ (4) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 12761) -> [17500 ps] WR @ (0, 952) -> [ 2500 ps] ACT @ (4, 10602) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11682) -> -[17500 ps] WR @ (0, 952) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [17500 ps] WR @ (4, 952) -> -[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5206) -> [10000 ps] ACT @ (0, 6286) -> -[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> -[10000 ps] WR @ (0, 944) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> -[17500 ps] WR @ (0, 944) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> -[10000 ps] WR @ (0, 936) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> -[17500 ps] WR @ (0, 936) -> [10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> -[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> -[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> -[10000 ps] WR @ (0, 928) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> -[17500 ps] WR @ (0, 928) -> [10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[17500 ps] WR @ (0, 920) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[17500 ps] WR @ (0, 920) -> [10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> -[10000 ps] ACT @ (4, 9915) -> [17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> -[10000 ps] ACT @ (4, 4519) -> [17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[17500 ps] WR @ (0, 912) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[17500 ps] WR @ (0, 912) -> [10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> -[10000 ps] ACT @ (4, 15507) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[17500 ps] WR @ (0, 904) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[17500 ps] WR @ (0, 904) -> [10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> -[10000 ps] ACT @ (4, 10111) -> [17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> -[10000 ps] ACT @ (4, 4715) -> [17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[17500 ps] WR @ (0, 896) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[17500 ps] WR @ (0, 896) -> [10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> -[10000 ps] ACT @ (4, 15703) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7069) -> [10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1673) -> [10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12661) -> [10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7265) -> [10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1869) -> [10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12857) -> [10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> -[10000 ps] WR @ (4, 824) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5695) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> -[10000 ps] WR @ (4, 816) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 299) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> -[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11287) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> -[10000 ps] WR @ (4, 808) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5891) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> -[10000 ps] WR @ (4, 800) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 495) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> -[10000 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 11483) -> [17500 ps] WR @ (0, 792) -> [ 2500 ps] ACT @ (4, 9324) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10404) -> -[17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> -[10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> -[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> -[17500 ps] WR @ (0, 784) -> [10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> -[10000 ps] ACT @ (4, 2849) -> [17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> -[17500 ps] WR @ (0, 784) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> -[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> -[10000 ps] ACT @ (4, 13837) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> -[17500 ps] WR @ (0, 776) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> -[17500 ps] WR @ (0, 776) -> [10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> -[10000 ps] ACT @ (4, 8441) -> [17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> -[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> -[17500 ps] WR @ (0, 768) -> [10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> -[10000 ps] ACT @ (4, 3045) -> [17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> -[17500 ps] WR @ (0, 768) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> -[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> -[10000 ps] ACT @ (4, 14033) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> -[17500 ps] WR @ (0, 760) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> -[17500 ps] WR @ (0, 760) -> [10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> -[10000 ps] ACT @ (4, 8637) -> [17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4320) -> [17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3241) -> [17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3) -> [10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15308) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14229) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10991) -> [10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9912) -> [17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8833) -> [17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5595) -> [10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4516) -> [17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3437) -> [17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 199) -> [10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15504) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14425) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11187) -> [10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10108) -> [17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9029) -> [17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 5791) -> [10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> -[10000 ps] WR @ (4, 688) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15013) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> -[10000 ps] WR @ (4, 680) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9617) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> -[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4221) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> -[10000 ps] WR @ (4, 672) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15209) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> -[10000 ps] WR @ (4, 664) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9813) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> -[10000 ps] WR @ (4, 656) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4417) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> -[10000 ps] WR @ (4, 656) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> -[17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> -[10000 ps] WR @ (4, 648) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> -[17500 ps] WR @ (4, 648) -> [10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> -[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> -[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> -[10000 ps] WR @ (4, 640) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> -[17500 ps] WR @ (4, 640) -> [10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> -[10000 ps] WR @ (4, 632) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> -[17500 ps] WR @ (4, 632) -> [10000 ps] WR @ (0, 632) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 2500 ps] ACT @ (4, 8046) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> -[17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> -[10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> -[17500 ps] WR @ (0, 624) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> -[17500 ps] WR @ (0, 624) -> [10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> -[10000 ps] ACT @ (4, 1571) -> [17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13638) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12559) -> [17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9321) -> [10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8242) -> [17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7163) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3925) -> [10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2846) -> [17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1767) -> [17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14913) -> [10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13834) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12755) -> [17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9517) -> [10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8438) -> [17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7359) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4121) -> [10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3042) -> [17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1963) -> [17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15109) -> [10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> -[10000 ps] WR @ (4, 552) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7947) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> -[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2551) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> -[10000 ps] WR @ (4, 544) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13539) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> -[10000 ps] WR @ (4, 536) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8143) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> -[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2747) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> -[10000 ps] WR @ (4, 528) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13735) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> -[10000 ps] WR @ (4, 520) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> -[17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> -[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> -[17500 ps] WR @ (4, 512) -> [10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> -[10000 ps] WR @ (4, 512) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> -[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> -[10000 ps] WR @ (4, 504) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> -[17500 ps] WR @ (4, 504) -> [10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> -[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> -[17500 ps] WR @ (4, 496) -> [10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> -[10000 ps] WR @ (4, 496) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> -[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> -[10000 ps] WR @ (4, 488) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> -[17500 ps] WR @ (4, 488) -> [10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> -[10000 ps] ACT @ (0, 8731) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> -[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> -[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> -[10000 ps] ACT @ (0, 3335) -> [17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> -[17500 ps] WR @ (4, 480) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> -[17500 ps] WR @ (4, 480) -> [10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> -[10000 ps] ACT @ (0, 14323) -> [17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> -[17500 ps] WR @ (4, 472) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> -[17500 ps] WR @ (4, 472) -> [10000 ps] WR @ (0, 472) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 7500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 464) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2451) -> [10000 ps] ACT @ (0, 3531) -> [17500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13439) -> [10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8043) -> [10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> -[10000 ps] WR @ (4, 416) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> -[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> -[10000 ps] WR @ (4, 408) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6473) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> -[10000 ps] WR @ (4, 400) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1077) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> -[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12065) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> -[10000 ps] WR @ (4, 392) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6669) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> -[10000 ps] WR @ (4, 384) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> -[17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> -[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> -[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> -[10000 ps] WR @ (4, 376) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> -[17500 ps] WR @ (4, 376) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> -[10000 ps] WR @ (4, 368) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> -[17500 ps] WR @ (4, 368) -> [10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> -[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> -[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> -[10000 ps] WR @ (4, 360) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> -[17500 ps] WR @ (4, 360) -> [10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> -[10000 ps] WR @ (4, 352) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> -[17500 ps] WR @ (4, 352) -> [10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> -[10000 ps] ACT @ (0, 1665) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> -[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> -[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> -[10000 ps] ACT @ (0, 12653) -> [17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> -[17500 ps] WR @ (4, 344) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> -[17500 ps] WR @ (4, 344) -> [10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> -[10000 ps] ACT @ (0, 7257) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> -[17500 ps] WR @ (4, 336) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> -[17500 ps] WR @ (4, 336) -> [10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> -[10000 ps] ACT @ (0, 1861) -> [17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> -[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> -[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> -[10000 ps] ACT @ (0, 12849) -> [17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> -[17500 ps] WR @ (4, 328) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> -[17500 ps] WR @ (4, 328) -> [10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> -[10000 ps] ACT @ (0, 7453) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> -[17500 ps] WR @ (4, 320) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> -[17500 ps] WR @ (4, 320) -> [10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> -[10000 ps] ACT @ (0, 2057) -> [17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14124) -> [17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13045) -> [17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9807) -> [10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [35000 ps] NOP -> -[10000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [17500 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> -[17500 ps] WR @ (0, 304) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 6569) -> -[17500 ps] WR @ (4, 304) -> [ 2500 ps] ACT @ (0, 4411) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15399) -> [10000 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> -[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12161) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> -[10000 ps] WR @ (0, 296) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> -[10000 ps] WR @ (0, 288) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1369) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> -[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> -[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> -[10000 ps] WR @ (0, 280) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> -[17500 ps] WR @ (0, 280) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> -[10000 ps] WR @ (0, 272) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> -[17500 ps] WR @ (0, 272) -> [10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> -[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> -[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> -[10000 ps] WR @ (0, 264) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> -[17500 ps] WR @ (0, 264) -> [10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> -[10000 ps] WR @ (0, 256) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> -[17500 ps] WR @ (0, 256) -> [10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> -[10000 ps] WR @ (0, 248) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> -[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> -[10000 ps] ACT @ (4, 12749) -> [17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[17500 ps] WR @ (0, 248) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> -[17500 ps] WR @ (0, 248) -> [10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> -[10000 ps] ACT @ (4, 7353) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[17500 ps] WR @ (0, 240) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> -[17500 ps] WR @ (0, 240) -> [10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> -[10000 ps] ACT @ (4, 1957) -> [17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> -[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> -[10000 ps] ACT @ (4, 12945) -> [17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[17500 ps] WR @ (0, 232) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> -[17500 ps] WR @ (0, 232) -> [10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> -[10000 ps] ACT @ (4, 7549) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[17500 ps] WR @ (0, 224) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> -[17500 ps] WR @ (0, 224) -> [10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> -[10000 ps] ACT @ (4, 2153) -> [17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[17500 ps] WR @ (0, 216) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> -[17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> -[10000 ps] ACT @ (4, 13141) -> [17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7745) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4507) -> [10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2349) -> [17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15495) -> [10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13337) -> [17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10099) -> [10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7941) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 4703) -> [10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3624) -> [17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2545) -> [17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15691) -> [10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14612) -> [17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13533) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10295) -> [10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> -[10000 ps] WR @ (4, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 5291) -> -[17500 ps] WR @ (4, 144) -> [ 2500 ps] ACT @ (0, 3133) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> -[10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> -[17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> -[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> -[17500 ps] WR @ (0, 136) -> [10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> -[10000 ps] WR @ (0, 136) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> -[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> -[10000 ps] WR @ (0, 128) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> -[17500 ps] WR @ (0, 128) -> [10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> -[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> -[17500 ps] WR @ (0, 120) -> [10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> -[10000 ps] WR @ (0, 120) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> -[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[17500 ps] WR @ (0, 112) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[17500 ps] WR @ (0, 112) -> [10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> -[10000 ps] ACT @ (4, 287) -> [17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[17500 ps] WR @ (0, 104) -> [10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> -[10000 ps] ACT @ (4, 11275) -> [17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[17500 ps] WR @ (0, 104) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> -[10000 ps] ACT @ (4, 5879) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[17500 ps] WR @ (0, 96) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[17500 ps] WR @ (0, 96) -> [10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> -[10000 ps] ACT @ (4, 483) -> [17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> -[10000 ps] ACT @ (4, 11471) -> [17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[17500 ps] WR @ (0, 88) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[17500 ps] WR @ (0, 88) -> [10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> -[10000 ps] ACT @ (4, 6075) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13825) -> [10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8429) -> [10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3033) -> [10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14021) -> [10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8625) -> [10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3229) -> [10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> -[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> -[10000 ps] WR @ (4, 8) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> -[10000 ps] WR @ (4, 0) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> -[25000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> -[ 2500 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (0, 8331) -> [10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 7500 ps] WR @ (3, 1008) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [17500 ps] WR @ (3, 1008) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 5093) -> [10000 ps] ACT @ (7, 5092) -> -[17500 ps] WR @ (7, 1008) -> [15000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2935) -> [12500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4013) -> -[17500 ps] WR @ (7, 1008) -> [ 2500 ps] ACT @ (4, 1855) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> -[ 2500 ps] ACT @ (3, 1855) -> [ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 7500 ps] WR @ (7, 1000) -> [ 2500 ps] ACT @ (4, 13922) -> [42500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> -[10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> -[10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> -[10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> -[10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> -[10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> -[10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> -[10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> -[10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> -[10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> -[10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> -[10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> [17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> [10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> -[10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> [17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> [17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> [10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> [17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> [10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> -[10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> [17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> [10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> -[10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> [17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> [17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> [10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> [17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> [10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> -[10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> [17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> -[35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> [10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> -[10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> -[17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> -[17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> -[10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> -[17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> -[10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> -[17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> -[10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> -[10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> -[17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> -[17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> -[10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> -[17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> -[17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> -[10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> -[10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> -[17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> -[17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> -[10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> -[17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> -[17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> -[10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> [10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [12500 ps] NOP -> [ 5000 ps] WR @ (7, 856) -> [10000 ps] WR @ (3, 856) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (3, 10290) -> [10000 ps] ACT @ (7, 9210) -> [ 7500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3814) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [10000 ps] WR @ (7, 848) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1656) -> [10000 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> [10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> [10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> -[10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> -[17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> -[17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> -[10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> -[17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> -[17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> -[ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> -[10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> -[10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> -[17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> -[10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> -[17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> -[17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> -[10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> -[10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> -[17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> -[10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> -[17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> -[10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> -[17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> -[17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> [ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> -[10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> -[15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> -[ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> -[10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> -[ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> -[ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> -[10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> -[ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> -[10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> -[15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> -[15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> -[10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> -[10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> -[15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> -[15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> -[10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> -[15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> -[15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> -[10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> -[10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> -[15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> -[15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> -[10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> [10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> [10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> [10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> [10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [ 2500 ps] NOP -> [12500 ps] RD @ (4, 856) -> -[10000 ps] RD @ (0, 856) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9620) -> -[15000 ps] RD @ (0, 856) -> [ 5000 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 986) -> [10000 ps] ACT @ (0, 16291) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> [10000 ps] ACT @ (0, 10895) -> -[ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> [15000 ps] RD @ (0, 840) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> [15000 ps] RD @ (0, 840) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> [10000 ps] ACT @ (0, 5499) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> [15000 ps] RD @ (0, 832) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> [15000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> [10000 ps] ACT @ (0, 103) -> -[ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> [15000 ps] RD @ (0, 824) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> [15000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> [10000 ps] ACT @ (0, 11091) -> -[ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> -[10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4616) -> -[10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> -[15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> -[15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15604) -> -[10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> -[15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> -[15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10208) -> -[10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4812) -> -[10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> -[15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> -[15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15800) -> -[10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> -[15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> -[15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10404) -> -[10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> [10000 ps] RD @ (4, 752) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> [10000 ps] RD @ (4, 744) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> [10000 ps] RD @ (4, 736) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> [10000 ps] RD @ (4, 728) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [15000 ps] RD @ (4, 720) -> -[10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> [10000 ps] RD @ (4, 720) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> [10000 ps] RD @ (4, 712) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> [ 5000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> [ 5000 ps] RD @ (4, 704) -> -[10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> [10000 ps] RD @ (4, 704) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> [10000 ps] RD @ (4, 696) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> [ 5000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> [ 5000 ps] RD @ (4, 688) -> -[10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> -[15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [15000 ps] RD @ (4, 688) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> [10000 ps] ACT @ (4, 12854) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [15000 ps] RD @ (4, 680) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [15000 ps] RD @ (4, 680) -> -[10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> [10000 ps] ACT @ (4, 7458) -> -[ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [15000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> [10000 ps] ACT @ (4, 2062) -> -[ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [15000 ps] RD @ (4, 672) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> [10000 ps] ACT @ (4, 13050) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [15000 ps] RD @ (4, 664) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [15000 ps] RD @ (4, 664) -> -[10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> [10000 ps] ACT @ (4, 7654) -> -[ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [15000 ps] RD @ (4, 656) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [15000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> [10000 ps] ACT @ (4, 2258) -> -[ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> -[10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12167) -> -[10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> -[15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> -[15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6771) -> -[10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> -[15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> -[15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1375) -> -[10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> -[15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> -[15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2650) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3730) -> [15000 ps] RD @ (0, 624) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1571) -> [10000 ps] ACT @ (0, 492) -> [ 5000 ps] RD @ (4, 624) -> [10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> [10000 ps] ACT @ (0, 15797) -> [15000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> [10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> [ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> [ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> [10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> [10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> [ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> [ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> [10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> [ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> [15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> [15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> [10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> [10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> [15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> [15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> [10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> [15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> [15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> [10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> [10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> -[10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> [15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> [15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> [10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> -[15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> -[10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> -[ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> -[ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> -[10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> -[ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> -[10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> -[ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> -[10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> -[15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> -[10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> -[15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> -[15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> -[10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> -[15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> -[10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> -[15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> -[10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> -[15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> -[15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> -[10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> -[15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> -[15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> -[10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> [10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> [10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> [10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> [ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> [ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> [10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> [10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> [ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> [ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> [10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> [ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> -[10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [15000 ps] RD @ (4, 416) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> [10000 ps] ACT @ (4, 15106) -> -[ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 14027) -> [15000 ps] RD @ (4, 408) -> [ 5000 ps] ACT @ (0, 11869) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> -[15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> -[10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5394) -> -[10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> -[15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16382) -> -[10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> -[15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10986) -> -[10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> -[15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> -[15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5590) -> -[10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> [10000 ps] RD @ (4, 344) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> [10000 ps] RD @ (4, 336) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> [10000 ps] RD @ (4, 328) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> [10000 ps] RD @ (4, 320) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> [15000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> [10000 ps] RD @ (4, 312) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> [ 5000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> [10000 ps] RD @ (4, 304) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> [ 5000 ps] RD @ (4, 304) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> [10000 ps] RD @ (4, 296) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> [ 5000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> [10000 ps] RD @ (4, 288) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> [ 5000 ps] RD @ (4, 288) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> -[15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [15000 ps] RD @ (4, 280) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [15000 ps] RD @ (4, 280) -> -[10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> [10000 ps] ACT @ (4, 8040) -> -[ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> [10000 ps] ACT @ (4, 2644) -> -[ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [15000 ps] RD @ (4, 272) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [15000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> [10000 ps] ACT @ (4, 13632) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [15000 ps] RD @ (4, 264) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [15000 ps] RD @ (4, 264) -> -[10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> [10000 ps] ACT @ (4, 8236) -> -[ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> [10000 ps] ACT @ (4, 2840) -> -[ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [15000 ps] RD @ (4, 256) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [15000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> [10000 ps] ACT @ (4, 13828) -> -[ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> -[10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> -[15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> -[15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7353) -> -[10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> -[15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> -[15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1957) -> -[10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12945) -> -[10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> -[15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> -[15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7549) -> -[10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> -[15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> -[15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2153) -> -[10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> -[15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> -[15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13141) -> -[10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [10000 ps] RD @ (4, 184) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [15000 ps] RD @ (4, 184) -> -[10000 ps] RD @ (0, 176) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4899) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> [10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> [15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> [15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> [10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> [15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> [15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> [10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> -[10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> [10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> -[10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> [15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> [15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> [10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> [15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> [15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> [10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> -[15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> -[10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> -[ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> -[ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> -[10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> -[ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> -[ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> -[10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> -[ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> -[10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> -[15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> -[15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> -[10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> -[15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> -[10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> -[15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> -[10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> -[15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> -[15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> -[10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> -[10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> -[15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> -[15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> -[10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> [10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> [10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> [10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> [10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> [ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> [10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> [10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> [ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> [ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> [10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> [ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> [10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> [10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> -[10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> [ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> -[10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> -[10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> -[10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> -[10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> -[10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> -[10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> -[10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> [10000 ps] NOP -> [ 7500 ps] ACT @ (0, 10685) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10684) -> -[15000 ps] RD @ (7, 1000) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 9606) -> -[10000 ps] ACT @ (7, 9605) -> [10000 ps] ACT @ (4, 8526) -> [ 5000 ps] RD @ (7, 1000) -> [ 5000 ps] ACT @ (3, 8526) -> [15000 ps] RD @ (3, 1000) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3130) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> -[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 5000 ps] RD @ (3, 992) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 2051) -> [10000 ps] ACT @ (4, 972) -> [ 5000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16277) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 5000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10881) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> -[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> -[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> -[10000 ps] ACT @ (3, 3326) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> -[15000 ps] RD @ (3, 976) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> -[15000 ps] RD @ (3, 976) -> [10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> -[10000 ps] ACT @ (3, 14314) -> [ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 12155) -> [10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11076) -> [15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9997) -> [15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 7839) -> [10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5680) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4601) -> [15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 2443) -> [10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 284) -> [15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15589) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13431) -> [10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 11272) -> [15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 10193) -> [15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 8035) -> [10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 5876) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4797) -> [15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 2639) -> [10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 480) -> [15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15785) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 13627) -> [10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> -[17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5385) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> -[10000 ps] RD @ (7, 896) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 16373) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 10977) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (7, 888) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 5581) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> -[10000 ps] RD @ (7, 880) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 185) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (7, 872) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11173) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> -[10000 ps] RD @ (7, 872) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> -[15000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (7, 864) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> -[ 5000 ps] RD @ (7, 864) -> [10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> -[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> -[ 5000 ps] RD @ (7, 856) -> [10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> -[10000 ps] RD @ (7, 856) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> -[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> -[10000 ps] RD @ (7, 848) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> -[ 5000 ps] RD @ (7, 848) -> [10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> -[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> -[10000 ps] RD @ (7, 840) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> -[ 5000 ps] RD @ (7, 840) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> -[10000 ps] ACT @ (3, 6169) -> [15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> -[15000 ps] RD @ (7, 832) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> -[15000 ps] RD @ (7, 832) -> [10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> -[10000 ps] ACT @ (7, 16077) -> [ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> -[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> -[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> -[10000 ps] ACT @ (7, 10681) -> [ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> -[15000 ps] RD @ (7, 824) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> -[15000 ps] RD @ (7, 824) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> -[10000 ps] ACT @ (7, 5285) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> -[15000 ps] RD @ (7, 816) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> -[15000 ps] RD @ (7, 816) -> [10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> -[10000 ps] ACT @ (7, 16273) -> [ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> -[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> -[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> -[10000 ps] ACT @ (7, 10877) -> [ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> -[15000 ps] RD @ (7, 808) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> -[15000 ps] RD @ (7, 808) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> -[10000 ps] ACT @ (7, 5481) -> [ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2244) -> [15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 1165) -> [15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 15390) -> [10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13232) -> [15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 12153) -> [15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 9994) -> [10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 7836) -> [15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6757) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 4598) -> [10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [67500 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 2440) -> [15000 ps] RD @ (3, 784) -> [ 5000 ps] ACT @ (7, 281) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> [10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> -[27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> -[27500 ps] PRE @ (3) -> --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 162720 ns -Time Done: 272280 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> -[ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 272420000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 273380 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:16 ; elapsed = 00:52:07 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1814 ; free virtual = 24675 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 3030440 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 19:44:03 2023... diff --git a/xsim/sim_busdelay625.log b/xsim/sim_busdelay625.log deleted file mode 100644 index c4959b0..0000000 --- a/xsim/sim_busdelay625.log +++ /dev/null @@ -1,262 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_controller -WARNING: [VRFC 10-3380] identifier 'WRITE_TO_PRECHARGE_DELAY' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:190] -WARNING: [VRFC 10-3380] identifier 'stage2_update' is used before its declaration [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v:705] -INFO: [VRFC 10-311] analyzing module mini_fifo -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_phy -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:279] -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:324] -WARNING: [VRFC 10-3401] illegal argument of type reg [packed dim count:1] in math function 'floor()', expected real type [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:367] -INFO: [VRFC 10-2263] Analyzing Verilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_top -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> [370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> INFO: [Common 17-41] Interrupt caught. Command should exit soon. -run: Time (s): cpu = 00:00:03 ; elapsed = 00:01:46 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1466 ; free virtual = 24759 -INFO: [Common 17-344] 'run' was cancelled -xsim: Time (s): cpu = 00:00:04 ; elapsed = 00:01:48 . Memory (MB): peak = 2833.148 ; gain = 844.395 ; free physical = 1466 ; free virtual = 24759 -INFO: [Common 17-344] 'source' was cancelled -xsim% adssss \ No newline at end of file diff --git a/xsim/sim_busdelay625_flybydelay0.log b/xsim/sim_busdelay625_flybydelay0.log deleted file mode 100644 index ff39ca8..0000000 --- a/xsim/sim_busdelay625_flybydelay0.log +++ /dev/null @@ -1,14263 +0,0 @@ -ddr3_dimm_micron_sim.sh - Script generated by export_simulation (Vivado v2021.2 (64-bit)-id) - -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3 -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm -INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" into library xil_defaultlib -INFO: [VRFC 10-311] analyzing module ddr3_dimm_micron_sim -Vivado Simulator v2021.2 -Copyright 1986-1999, 2001-2021 Xilinx, Inc. All Rights Reserved. -Running: /tools/Xilinx/Vivado/2021.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L uvm -L unisims_ver -L unimacro_ver -L secureip --snapshot ddr3_dimm_micron_sim xil_defaultlib.ddr3_dimm_micron_sim xil_defaultlib.glbl -log elaborate.log -Starting static elaboration -Pass Through NonSizing Optimizer -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:204] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:135] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:156] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:157] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:158] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 5 for port 'CNTVALUEIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:159] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:160] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LD' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:161] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:163] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:165] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:250] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:275] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:276] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:281] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:283] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:319] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:325] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:326] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:374] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:375] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'TCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:426] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:427] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:452] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:453] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:458] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:460] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:497] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:498] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CLKIN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:499] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:501] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:504] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:506] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:536] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:575] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CINVCTRL' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:576] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'INC' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:580] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'LDPIPEEN' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:582] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'REGRST' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:583] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:631] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:632] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE1' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:700] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'CE2' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:701] -WARNING: [VRFC 10-3091] actual bit length 32 differs from formal bit length 1 for port 'OCE' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v:747] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:163] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'ck_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:164] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'cke' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:165] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 's_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:166] -WARNING: [VRFC 10-3091] actual bit length 14 differs from formal bit length 16 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:171] -WARNING: [VRFC 10-3091] actual bit length 1 differs from formal bit length 2 for port 'odt' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:172] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:173] -WARNING: [VRFC 10-3091] actual bit length 8 differs from formal bit length 18 for port 'dqs_n' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:174] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:203] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:204] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:205] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:206] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:207] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:208] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:209] -WARNING: [VRFC 10-3091] actual bit length 16 differs from formal bit length 14 for port 'addr' [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm.v:210] -WARNING: [VRFC 10-5021] port 'scl' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v:161] -WARNING: [VRFC 10-5021] port 'i_controller_dm' is not connected on this instance [/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v:119] -Completed static elaboration -Starting simulation data flow analysis -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_top.v" Line 3. Module ddr3_top(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_controller.v" Line 37. Module ddr3_controller(CONTROLLER_CLK_PERIOD=10.0,OPT_LOWPOWER=1'b1,OPT_BUS_ABORT=1'b1) doesn't have a timescale but at least one module in design has a timescale. -WARNING: [XSIM 43-4099] "/home/angelo/Desktop/switch_fpga/DDR3_Controller/rtl/ddr3_phy.v" Line 3. Module ddr3_phy(CONTROLLER_CLK_PERIOD=10.0,DDR3_CLK_PERIOD=2.5) doesn't have a timescale but at least one module in design has a timescale. -Completed simulation data flow analysis -Time Resolution for simulation is 1ps -Compiling module xil_defaultlib.ddr3_controller(CONTROLLER_CLK_P... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_OQ="SDR",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="SDR",DAT... -Compiling module unisims_ver.OBUFDS -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.IOBUF(IOSTANDARD="SSTL15",SLEW="... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.OBUF(SLEW="FAST") -Compiling module unisims_ver.ODELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.OSERDESE2(DATA_RATE_TQ="BUF",DAT... -Compiling module unisims_ver.IOBUFDS(IOSTANDARD="DIFF_SSTL15"... -Compiling module unisims_ver.IDELAYE2(HIGH_PERFORMANCE_MODE="... -Compiling module unisims_ver.ISERDESE2(DATA_WIDTH=8,INTERFACE... -Compiling module unisims_ver.IDELAYCTRL_default -Compiling module xil_defaultlib.ddr3_phy(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_top(CONTROLLER_CLK_PERIOD=1... -Compiling module xil_defaultlib.ddr3_default -Compiling module xil_defaultlib.ddr3_dimm_default -Compiling module xil_defaultlib.ddr3_dimm_micron_sim -Compiling module xil_defaultlib.glbl -Built simulation snapshot ddr3_dimm_micron_sim - -****** xsim v2021.2 (64-bit) - **** SW Build 3367213 on Tue Oct 19 02:47:39 MDT 2021 - **** IP Build 3369179 on Thu Oct 21 08:25:16 MDT 2021 - ** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved. - -source xsim.dir/ddr3_dimm_micron_sim/xsim_script.tcl -# xsim {ddr3_dimm_micron_sim} -autoloadwcfg -tclbatch {cmd.tcl} -key {Behavioral:sim_1:Functional:ddr3_dimm_micron_sim} -Time resolution is 1 ps -source cmd.tcl -## set curr_wave [current_wave_config] -## if { [string length $curr_wave] == 0 } { -## if { [llength [get_objects]] > 0} { -## add_wave / -## set_property needs_save false [current_wave_config] -## } else { -## send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." -## } -## } -## run -all -Test ns_to_cycles() function: - ns_to_cycles(15) = 3 = 2 [exact] - ns_to_cycles(14.5) = 3 = 2 [round-off] - ns_to_cycles(11) = 3 = 2 [round-up] - -Test nCK_to_cycles() function: - ns_to_cycles(16) = 4 = 4 [exact] - ns_to_cycles(15) = 4 = 4 [round-off] - ns_to_cycles(13) = 4 = 4 [round-up] - -Test ns_to_nCK() function: - ns_to_cycles(15) = 12 = 6 [exact] - ns_to_cycles(14.875) = 12 = 6 [round-off] - ns_to_cycles(13.875) = 12 = 6 [round-up] - ns_to_nCK(tRCD) = 11 = 6 [WRONG] - tRTP = 7.5 = 10.000000 - ns_to_nCK(tRTP) = 6= 4.000000 [WRONG] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test nCK_to_ns() function: - ns_to_cycles(4) = 5 = 10 [exact] - ns_to_cycles(14.875) = 4 = 8 [round-off] - ns_to_cycles(13.875) = 7 = 13 [round-up] - -Test $floor() function: - $floor(5/2) = 2.5 = 2 - $floor(9/4) = 2.25 = 2 - $floor(9/4) = 2 = 2 - $floor(9/5) = 1.8 = 1 - - -DELAY_COUNTER_WIDTH = 16 -DELAY_SLOT_WIDTH = 19 -serdes_ratio = 4 -wb_addr_bits = 24 -wb_data_bits = 512 -wb_sel_bits = 64 - - -READ_SLOT = 2 -WRITE_SLOT = 3 -ACTIVATE_SLOT = 0 -PRECHARGE_SLOT = 1 - - -DELAYS: - ns_to_nCK(tRCD): 6 - ns_to_nCK(tRP): 6 - ns_to_nCK(tRTP): 4 - tCCD: 4 - (CL_nCK + tCCD + 3'd2 - CWL_nCK): 7 - (CWL_nCK + 3'd4 + ns_to_nCK(tWR)): 15 - (CWL_nCK + 3'd4 + ns_to_nCK(tWTR)): 13 - $signed(4'b1100)>>>4: 1111 - - -PRECHARGE_TO_ACTIVATE_DELAY = 3 = 1 -ACTIVATE_TO_WRITE_DELAY = 3 = 0 -ACTIVATE_TO_READ_DELAY = 2 = 0 -READ_TO_WRITE_DELAY = 2 = 1 -READ_TO_READ_DELAY = 0 = 0 -READ_TO_PRECHARGE_DELAY = 1 =1 -WRITE_TO_WRITE_DELAY = 0 = 0 -WRITE_TO_READ_DELAY = 4 = 3 -WRITE_TO_PRECHARGE_DELAY = 5 = 4 -STAGE2_DATA_DEPTH = 2 = 2 -READ_ACK_PIPE_WIDTH = 6 -ddr3_dimm_micron_sim.ddr3_dimm.U1.file_io_open: at time 0 WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U2.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U3.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U4.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U6.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U7.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U8.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -ddr3_dimm_micron_sim.ddr3_dimm.U9.file_io_open: at time 0.0 ps WARNING: no +model_data option specified, using /tmp. -[x ps] MRS -> [ 7500 ps] MRS -> ddr3_dimm_micron_sim.ddr3_dimm.U1.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U2.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U3.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U4.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U6.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U7.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U8.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -ddr3_dimm_micron_sim.ddr3_dimm.U9.reset at time 301949.0 ps WARNING: 200 us is required before RST_N goes inactive. -[195000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task at time 813225.0 ps WARNING: 500 us is required after RST_N goes inactive before CKE goes active. -[510000 ps] NOP -> [370000 ps] MRS -> -ddr3_dimm_micron_sim.ddr3_dimm.U1.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U2.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U3.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U4.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U6.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U7.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U8.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -ddr3_dimm_micron_sim.ddr3_dimm.U9.cmd_task: at time 1185725.0 ps WARNING: Load Mode 2 Auto Self Refresh is not modeled -[10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> [40000 ps] ZQC -> -[1290000 ps] PRE @ (0) -> [30000 ps] MRS -> [10000 ps] NOP -> [40000 ps] NOP -> [262500 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[480000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [120000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> -[130000 ps] RD @ (0, 0) -> [130000 ps] RD @ (0, 0) -> [247500 ps] MRS -> [10000 ps] MRS -> [10000 ps] NOP -> -[110000 ps] NOP -> ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27472027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27474527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27477027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27479527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27482027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27484527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27487027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27489527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27492027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27494527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27622105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27624605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27627105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27629605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27632105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27634605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27637105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27639605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27642105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 27644605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 27944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 28994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29573225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29575725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29578225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29580725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29583225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29585725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29588225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29590725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29593225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29595725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29723225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29725725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29728225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29730725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29733225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29735725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29738225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29740725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29743225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.main: at time 29745725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 29894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 29895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30322027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30324527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30327027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30329527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30332027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30334527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30337027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30339527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30342027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30344527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30472105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30474605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30477105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30479605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30482105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30484605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30487105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30489605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30492105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 30494605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 30944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 30945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 31994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 31995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32423225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32425725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32428225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32430725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32433225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32435725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32438225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32440725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32443225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32445725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32573225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32575725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32578225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32580725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32583225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32585725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32588225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32590725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32593225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.main: at time 32595725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 32894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 32895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 32895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33172027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33174527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33177027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33179527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33182027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33184527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33187027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33189527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33192027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33194527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33322105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33324605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33327105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33329605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33332105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33334605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33337105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33339605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33342105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 33344605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 33944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 33945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 33945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 34994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 34995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 34995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35273225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35275725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35278225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35280725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35283225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35285725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35288225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35290725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35293225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35295725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35423225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35425725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35428225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35430725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35433225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35435725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35438225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35440725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35443225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.main: at time 35445725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 35894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 35895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36022027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36024527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36027027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36029527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36032027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36034527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36037027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36039527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36042027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36044527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36172105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36174605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36177105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36179605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36182105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36184605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36187105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36189605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36192105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 36194605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 36944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 36945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 37994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 37995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38123225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38125725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38128225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38130725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38133225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38135725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38138225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38140725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38143225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38145725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38273225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38275725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38278225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38280725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38283225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38285725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38288225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38290725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38293225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.main: at time 38295725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38872027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38874527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38877027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38879527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38882027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38884527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38887027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38889527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38892027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 38894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 38894527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 38895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39022105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39024605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39027105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39029605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39032105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39034605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39037105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39039605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39042105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 39044605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 39944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 39945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40973225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40975725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40978225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40980725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40983225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40985725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40988225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40990725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40993225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 40994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 40995725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 40995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41123225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41125725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41128225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41130725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41133225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41135725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41138225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41140725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41143225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.main: at time 41145725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41722027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41724527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41727027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41729527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41732027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41734527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41737027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41739527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41742027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41744527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41872105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41874605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41877105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41879605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41882105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41884605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41887105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41889605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41892105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 41894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 41894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 41894605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 41895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 42944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 42944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 42945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43823225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43825725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43828225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43830725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43833225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43835725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43838225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43840725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43843225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43845725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43973225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43975725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43978225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43980725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43983225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43985725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43988225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43990725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43993225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 43994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 43994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.main: at time 43995725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 43995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44421975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44424475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44426975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44429475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44431975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44434475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44436975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44439475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44441975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 44444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44444475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44571975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44572027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44574475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44574527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44576975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44577027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44579475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44579527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44581975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44582027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44584475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44584527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44586975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44587027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44589475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44589527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44591975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44592027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44594475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44594527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44721975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44722105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44724475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44724605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44726975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44727105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44729475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44729605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44731975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44732105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44734475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44734605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44736975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44737105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44739475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44739605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44741975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44742105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44744475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 44744605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44871975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44874475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44876975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44879475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44881975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44884475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44886975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44889475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44891975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 44894475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 44895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45021975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45024475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45026975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45029475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45031975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45034475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45036975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45039475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45041975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45044475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45171975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45174475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45176975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45179475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45181975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45184475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45186975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45189475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45191975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45194475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45321975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45324475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45326975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45329475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45331975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45334475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45336975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45339475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45341975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45344475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45471975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45474475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45476975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45479475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45481975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45484475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45486975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45489475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45491975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45494475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45621975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45624475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45626975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45629475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45631975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45634475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45636975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45639475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45641975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45644475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45771975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45774475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45776975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45779475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45781975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45784475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45786975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45789475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45791975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45794475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45921975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45924475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45926975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45929475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45931975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45934475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45936975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45939475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45941975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 45944475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 45945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46071975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46074475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46076975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46079475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46081975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46084475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46086975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46089475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46091975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46094475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46221975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46224475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46226975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46229475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46231975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46234475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46236975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46239475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46241975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46244475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46371975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46374475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46376975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46379475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46381975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46384475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46386975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46389475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46391975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46394475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46521975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46524475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46526975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46529475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46531975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46534475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46536975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46539475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46541975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46544475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46671975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46673225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46674475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46675725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46676975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46678225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46679475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46680725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46681975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46683225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46684475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46685725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46686975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46688225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46689475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46690725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46691975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46693225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46694475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46695725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46821975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46823225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46824475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46825725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46826975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46828225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46829475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46830725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46831975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46833225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46834475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46835725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46836975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46838225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46839475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46840725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46841975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46843225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46844475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.main: at time 46845725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46971975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46973275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46974475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46975775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46976975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46978275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46979475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46980775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46981975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46983275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46984475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46985775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46986975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46988275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46989475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46990775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46991975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46993275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 46994475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 46995775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47121975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47123275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47124475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47125775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47126975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47128275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47129475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47130775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47131975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47133275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47134475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47135775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47136975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47138275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47139475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47140775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47141975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47143275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47144475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47145775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47271975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47273275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47274475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47275775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47276975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47278275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47279475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47280775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47281975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47283275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47284475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47285775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47286975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47288275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47289475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47290775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47291975.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47293275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 47294475.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47295775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47422027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47423275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47424527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47425775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47427027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47428275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47429527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47430775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47432027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47433275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47434527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47435775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47437027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47438275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47439527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47440775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47442027.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47443275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47444527.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47445775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47572105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47573275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47574605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47575775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47577105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47578275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47579605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47580775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47582105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47583275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47584605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47585775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47587105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47588275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47589605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47590775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47592105.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47593275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 47594605.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47595775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47723275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47725775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47728275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47730775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47733275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47735775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47738275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47740775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47743275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47745775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47873275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47875775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47878275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47880775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47883275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47885775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47888275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47890775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47893275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 47895775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48023275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48025775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48028275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48030775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48033275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48035775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48038275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48040775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48043275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48045775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48173275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48175775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48178275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48180775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48183275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48185775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48188275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48190775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48193275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48195775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48323275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48325775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48328275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48330775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48333275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48335775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48338275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48340775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48343275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48345775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48473275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48475775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48478275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48480775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48483275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48485775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48488275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48490775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48493275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48495775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48623275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48625775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48628275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48630775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48633275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48635775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48638275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48640775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48643275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48645775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48773275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48775775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48778275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48780775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48783275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48785775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48788275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48790775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48793275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48795775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48923275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48925775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48928275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48930775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48933275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48935775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48938275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48940775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48943275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 48945775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49073275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49075775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49078275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49080775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49083275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49085775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49088275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49090775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49093275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49095775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49223275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49225775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49228275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49230775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49233275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49235775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49238275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49240775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49243275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49245775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49373275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49375775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49378275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49380775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49383275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49385775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49388275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49390775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49393275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49395775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49523225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49523275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49525725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49525775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49528225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49528275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49530725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49530775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49533225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49533275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49535725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49535775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49538225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49538275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49540725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49540775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49543225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49543275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49545725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49545775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49673225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49673275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49675725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49675775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49678225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49678275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49680725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49680775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49683225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49683275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49685725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49685775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49688225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49688275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49690725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49690775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49693225.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49693275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.main: at time 49695725.0 ps WARNING: tWLH violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49695775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49823275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49825775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49828275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49830775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49833275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49835775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49838275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49840775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49843275.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U1.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U2.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U3.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U4.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U6.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U7.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U8.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -ddr3_dimm_micron_sim.ddr3_dimm.U9.dqs_pos_timing_check: at time 49845775.0 ps WARNING: tWLS violation on DQS bit 0 positive edge. Indeterminate CK capture is possible. -[22670000 ps] MRS -> [10000 ps] NOP -> [40000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [37500 ps] ACT @ (0, 0) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [37500 ps] RD @ (0, 0) -> -[202500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 0) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 0) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 0) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 0) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> -[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (5, 0) -> [17500 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 0) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> -[10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> -[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 0) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 1) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 1) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 0) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 0) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> -[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (2, 0) -> [15000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 0) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 0) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 0) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 0) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 0) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 1) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 1) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: FIRST ROW -Number of Operations: 2304 -Time Started: 50650 ns -Time Done: 74740 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -[27500 ps] NOP -> FAILED: Address = 1150, expected data = cbcfbe97cbceb097cbcda297cbcc9497cbcb8897cbca7a97cbc96c97cbc85e97cbc75097cbc64297cbc53497cbc42697cbc31897cbc20a97cbc0fe97cbbff097, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 74820000.0 ps -[70000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [27500 ps] ACT @ (0, 8192) -> -[17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> -[10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> -[10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> -[10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> -[10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> -[10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> -[10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> -[10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> -[10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> -[10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> -[10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> -[10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> -[10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> -[10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> -[10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> -[10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> -[10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> -[10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> -[10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> -[10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> -[10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> -[10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> -[10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> -[10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> -[10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8192) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> -[10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> -[10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> [10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> -[10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> [10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> -[10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> [10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> -[10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> [10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> -[10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> [10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> -[10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> [10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> -[10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> [10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> -[10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> [10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> -[10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> [10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> -[10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> [10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> -[10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> [10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> -[10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> [10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> -[10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> [10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> -[10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> [10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> -[10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> [10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> -[10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> [10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> -[10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> [10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> -[10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> [10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> -[10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> [10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> -[10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> [10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> -[10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> [10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> -[10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> [10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> -[10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> [10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> -[10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> [10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> -[10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 8192) -> [ 7500 ps] WR @ (1, 976) -> [10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> -[10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> [10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> -[10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> [10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> -[10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> [10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> -[10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> [10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> -[10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> [10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> -[10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> [10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> -[10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> [10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> -[10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> [10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> -[10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> [10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> -[10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> [10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> -[10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> [10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> -[10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> [10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> -[10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> [10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> -[10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> [10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> -[10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> [10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> -[10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> [10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> -[10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> [10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> -[10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> [10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> -[10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> [10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> -[10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> [10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> -[10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> [10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> -[10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> [10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> -[10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> [10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> -[10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> [10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> -[10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> [10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> -[ 2500 ps] ACT @ (3, 8192) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> [10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> -[10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> [10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> -[10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> [10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> -[10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> [10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> -[10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> [10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> -[10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> [10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> -[10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> [10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> -[10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> [10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> -[10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> [10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> -[10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> [10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> -[10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> [10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> -[10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> [10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> -[10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> [10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> -[10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> [10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> -[10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> [10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> -[10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> [10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> -[10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> [10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> -[10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> [10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> -[10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> [10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> -[10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> [10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> -[10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> [10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> -[10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> [10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> -[10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> [10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> -[10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> [10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> -[10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> [10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> -[10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> [10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 8192) -> -[ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> [10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> -[10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> [10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> -[10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> [10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> -[10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> [10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> -[10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> [10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> -[10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> [10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> -[10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> [10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> -[10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> [10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> -[10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> [10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> -[10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> [10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> -[10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> [10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> -[10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> [10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> -[10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> [10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> -[10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> [10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> -[10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> [10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> -[10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> [10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> -[10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> [10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> -[10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> [10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> -[10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> [10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> -[10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> [10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> -[10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> [10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> -[10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> [10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> -[10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> [10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> -[10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> [10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> -[10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> [10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> -[10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> [ 2500 ps] ACT @ (5, 8192) -> [ 7500 ps] WR @ (4, 976) -> -[10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> [10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> -[10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> [10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> -[10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> [10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> -[10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> [10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> -[10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> [10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> -[10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> [10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> -[10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> [10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> -[10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> [10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> -[10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> [10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> -[10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> [10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> -[10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> [10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> -[10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> [10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> -[10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> [10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> -[10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> [10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> -[10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> [10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> -[10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> [10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> -[10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> [10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> -[10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> [10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> -[10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> [10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> -[10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> [10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> -[10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> [10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> -[10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> [10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> -[10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> [10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> -[10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> [10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> -[10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> [10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> -[10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 8192) -> [ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> -[10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> [10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> -[10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> [10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> -[10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 72) -> -[10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (6, 8192) -> [17500 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> [10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> -[10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> [10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> -[10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> [10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> -[10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> [10000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> -[10000 ps] WR @ (6, 248) -> [10000 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> [10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> -[10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> [10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> -[10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> [10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> -[10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> [10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> -[10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> [10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> -[10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> [10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> -[10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> [10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> -[10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> [10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> -[10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> [10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> -[10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> [10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> -[10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> [10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> -[10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> [10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> -[10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> [10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> -[10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> [10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> -[10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> [10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> -[10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> [10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> -[10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> [10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> -[10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> [10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> -[10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 8192) -> [ 7500 ps] WR @ (6, 976) -> [10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> -[10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> [10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> -[10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> [10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> -[10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> [10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> -[10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> [10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> -[10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> [10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> -[10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> [10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> -[10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> [10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> -[10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> [10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> -[10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> [10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> -[10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> [10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> -[10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> [10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> -[10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> [10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> -[10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> [10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> -[10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> [10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> -[10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> [10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> -[10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> [10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> -[10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> [10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> -[10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> [10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> -[10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> [10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> -[10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> [10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> -[10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> [10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> -[10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> [10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> -[10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> [10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> -[10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> [10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> -[10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> [10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> -[ 2500 ps] ACT @ (0, 8193) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> [10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> -[10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> -[10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 8193) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8192) -> [15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> [ 5000 ps] ACT @ (1, 8192) -> [ 5000 ps] RD @ (0, 992) -> -[10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> [10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> -[10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> [10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> -[10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> [10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> -[10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> [10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> -[10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> [10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> -[10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> [10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> -[10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> [10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> -[10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> [10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> -[10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> [10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> -[10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> [10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> -[10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> [10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> -[10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> [10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> -[10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> [10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> -[10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> [10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> -[10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> [10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> -[10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> [10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> -[10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> [10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> -[10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> [10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> -[10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> [10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> -[10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> [10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> -[10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> [10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> -[10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> [10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> -[10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> [10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> -[10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> [10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> -[10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> [10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> -[ 5000 ps] ACT @ (2, 8192) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> [10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> -[10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> [10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> -[10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> [10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> -[10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> [10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> -[10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> [10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> -[10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> [10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> -[10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> [10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> -[10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> [10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> -[10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> [10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> -[10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> [10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> -[10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> [10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> -[10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> [10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> -[10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> [10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> -[10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> [10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> -[10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> [10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> -[10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> [10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> -[10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> [10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> -[10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> [10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> -[10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> [10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> -[10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> [10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> -[10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> [10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> -[10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> [10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> -[10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> [10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> -[10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> [10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> -[10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> [10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> -[10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> [10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 8192) -> -[ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> [10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> -[10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> [10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> -[10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> [10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> -[10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> [10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> -[10000 ps] RD @ (3, 112) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> [10000 ps] RD @ (3, 136) -> -[67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (3, 8192) -> [15000 ps] RD @ (3, 144) -> -[10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> [10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> -[10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> [10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> -[10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> [10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> -[10000 ps] RD @ (3, 272) -> [10000 ps] RD @ (3, 280) -> [10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [10000 ps] RD @ (3, 304) -> -[10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> [10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> -[10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> [10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> -[10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> [10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> -[10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> [10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> -[10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> [10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> -[10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> [10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> -[10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> [10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> -[10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> [10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> -[10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> [10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> -[10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> [10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> -[10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> [10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> -[10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> [10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> -[10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> [10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> -[10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> [10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> -[10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> [10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> -[10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> [10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> -[10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> [ 5000 ps] ACT @ (4, 8192) -> [ 5000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> [10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> -[10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> [10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> -[10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> [10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> -[10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> [10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> -[10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> [10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> -[10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> [10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> -[10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> [10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> -[10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> [10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> -[10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> [10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> -[10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> [10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> -[10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> [10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> -[10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> [10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> -[10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> [10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> -[10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> [10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> -[10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> [10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> -[10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> [10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> [10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> -[10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> [10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> -[10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> [10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> -[10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> [10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> -[10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> [10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> -[10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> [10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> -[10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> [10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> -[10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> [10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> -[10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> [10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> -[10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 8192) -> [ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> -[10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> [10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> -[10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> [10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> -[10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> [10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> -[10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> [10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> -[10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> [10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> -[10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> [10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> -[10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> [10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> -[10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> [10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> -[10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> [10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> -[10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> [10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> -[10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> [10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> -[10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> [10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> -[10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> [10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> -[10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> [10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> -[10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> [10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> -[10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> [10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> -[10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> [10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> -[10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> [10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> -[10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> [10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> -[10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> [10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> -[10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> [10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> -[10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> [10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> -[10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> [10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> -[10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> [10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> -[10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> [10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> -[10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 8192) -> [ 5000 ps] RD @ (5, 976) -> [10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> -[10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> [10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> -[10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> [10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> -[10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> [10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> -[10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> [10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> -[10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> [10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> -[10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> [10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> -[10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> [10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> -[10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> [10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> -[10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> [10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> -[10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> [10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> -[10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> [10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> -[10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> [10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> -[10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> [10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> -[10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> [10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> -[10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> [10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> -[10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> [10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> -[10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> [10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> -[10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> [10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> -[10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> [10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> -[10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> [10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> -[10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> [10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> -[10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> [10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> -[10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> [10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> -[10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> [10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> -[10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> [10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> -[ 5000 ps] ACT @ (7, 8192) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> [10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> -[10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> [10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> -[10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> [10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> -[10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> [10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> -[10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> [10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> -[10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> [10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> -[10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> [10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> -[10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> [10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> -[10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> [10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> -[10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> [10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> -[10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> [10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> -[10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> [10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> -[10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> [10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> -[10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> [10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> -[10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> [10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> -[10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> [10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> -[10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> [10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> -[10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> [10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> -[10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> [10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> -[10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> [10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> -[10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> [10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> -[10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> [10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> [10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> [10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> -[10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> [10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> -[10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> [10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 8193) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> [10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> -[10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> -[10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> -[10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> -[10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> -[10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> -[10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> -[10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> -[10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> -[10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> -[10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> -[10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> -[10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> -[10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> -[10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> -[10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> -[10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 5000 ps] ACT @ (1, 8193) -> [ 5000 ps] RD @ (0, 976) -> -[10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: MIDDLE ROW -Number of Operations: 2304 -Time Started: 74840 ns -Time Done: 99330 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -FAILED: Address = 8389758, expected data = 33cfbf6733ceb16733cda36733cc956733cb896733ca7b6733c96d6733c85f6733c7516733c6436733c5356733c4276733c3196733c20b6733c0ff6733bff167, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 99410000.0 ps -[97500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> -[10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> [10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> -[10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> [10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> -[10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (0, 128) -> -[10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 16383) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> [10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> -[10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> [10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> -[10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> [10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> -[10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> [10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> -[10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> [10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> -[10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> [10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> -[10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> [10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> -[10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> [10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> -[10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> [10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> -[10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> [10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> -[10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> [10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> -[10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> [10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> -[10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> [10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> -[10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> [10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> -[10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> [10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> -[10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> [10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> -[10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> [10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> -[10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> [10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> -[10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> [10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> -[10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> [10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> -[10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> [10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 16383) -> -[ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> [10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> -[10000 ps] WR @ (0, 1016) -> [10000 ps] WR @ (1, 0) -> [10000 ps] WR @ (1, 8) -> [10000 ps] WR @ (1, 16) -> [10000 ps] WR @ (1, 24) -> -[10000 ps] WR @ (1, 32) -> [10000 ps] WR @ (1, 40) -> [10000 ps] WR @ (1, 48) -> [10000 ps] WR @ (1, 56) -> [10000 ps] WR @ (1, 64) -> -[10000 ps] WR @ (1, 72) -> [10000 ps] WR @ (1, 80) -> [10000 ps] WR @ (1, 88) -> [10000 ps] WR @ (1, 96) -> [10000 ps] WR @ (1, 104) -> -[10000 ps] WR @ (1, 112) -> [10000 ps] WR @ (1, 120) -> [10000 ps] WR @ (1, 128) -> [10000 ps] WR @ (1, 136) -> [10000 ps] WR @ (1, 144) -> -[10000 ps] WR @ (1, 152) -> [10000 ps] WR @ (1, 160) -> [10000 ps] WR @ (1, 168) -> [10000 ps] WR @ (1, 176) -> [10000 ps] WR @ (1, 184) -> -[10000 ps] WR @ (1, 192) -> [10000 ps] WR @ (1, 200) -> [10000 ps] WR @ (1, 208) -> [10000 ps] WR @ (1, 216) -> [10000 ps] WR @ (1, 224) -> -[10000 ps] WR @ (1, 232) -> [10000 ps] WR @ (1, 240) -> [10000 ps] WR @ (1, 248) -> [10000 ps] WR @ (1, 256) -> [10000 ps] WR @ (1, 264) -> -[10000 ps] WR @ (1, 272) -> [10000 ps] WR @ (1, 280) -> [10000 ps] WR @ (1, 288) -> [10000 ps] WR @ (1, 296) -> [10000 ps] WR @ (1, 304) -> -[10000 ps] WR @ (1, 312) -> [10000 ps] WR @ (1, 320) -> [10000 ps] WR @ (1, 328) -> [10000 ps] WR @ (1, 336) -> [10000 ps] WR @ (1, 344) -> -[10000 ps] WR @ (1, 352) -> [10000 ps] WR @ (1, 360) -> [10000 ps] WR @ (1, 368) -> [10000 ps] WR @ (1, 376) -> [10000 ps] WR @ (1, 384) -> -[10000 ps] WR @ (1, 392) -> [10000 ps] WR @ (1, 400) -> [10000 ps] WR @ (1, 408) -> [10000 ps] WR @ (1, 416) -> [10000 ps] WR @ (1, 424) -> -[10000 ps] WR @ (1, 432) -> [10000 ps] WR @ (1, 440) -> [10000 ps] WR @ (1, 448) -> [10000 ps] WR @ (1, 456) -> [10000 ps] WR @ (1, 464) -> -[10000 ps] WR @ (1, 472) -> [10000 ps] WR @ (1, 480) -> [10000 ps] WR @ (1, 488) -> [10000 ps] WR @ (1, 496) -> [10000 ps] WR @ (1, 504) -> -[10000 ps] WR @ (1, 512) -> [10000 ps] WR @ (1, 520) -> [10000 ps] WR @ (1, 528) -> [10000 ps] WR @ (1, 536) -> [10000 ps] WR @ (1, 544) -> -[10000 ps] WR @ (1, 552) -> [10000 ps] WR @ (1, 560) -> [10000 ps] WR @ (1, 568) -> [10000 ps] WR @ (1, 576) -> [10000 ps] WR @ (1, 584) -> -[10000 ps] WR @ (1, 592) -> [10000 ps] WR @ (1, 600) -> [10000 ps] WR @ (1, 608) -> [10000 ps] WR @ (1, 616) -> [10000 ps] WR @ (1, 624) -> -[10000 ps] WR @ (1, 632) -> [10000 ps] WR @ (1, 640) -> [10000 ps] WR @ (1, 648) -> [10000 ps] WR @ (1, 656) -> [10000 ps] WR @ (1, 664) -> -[10000 ps] WR @ (1, 672) -> [10000 ps] WR @ (1, 680) -> [10000 ps] WR @ (1, 688) -> [10000 ps] WR @ (1, 696) -> [10000 ps] WR @ (1, 704) -> -[10000 ps] WR @ (1, 712) -> [10000 ps] WR @ (1, 720) -> [10000 ps] WR @ (1, 728) -> [10000 ps] WR @ (1, 736) -> [10000 ps] WR @ (1, 744) -> -[10000 ps] WR @ (1, 752) -> [10000 ps] WR @ (1, 760) -> [10000 ps] WR @ (1, 768) -> [10000 ps] WR @ (1, 776) -> [10000 ps] WR @ (1, 784) -> -[10000 ps] WR @ (1, 792) -> [10000 ps] WR @ (1, 800) -> [10000 ps] WR @ (1, 808) -> [10000 ps] WR @ (1, 816) -> [10000 ps] WR @ (1, 824) -> -[10000 ps] WR @ (1, 832) -> [10000 ps] WR @ (1, 840) -> [10000 ps] WR @ (1, 848) -> [10000 ps] WR @ (1, 856) -> [10000 ps] WR @ (1, 864) -> -[10000 ps] WR @ (1, 872) -> [10000 ps] WR @ (1, 880) -> [10000 ps] WR @ (1, 888) -> [10000 ps] WR @ (1, 896) -> [10000 ps] WR @ (1, 904) -> -[10000 ps] WR @ (1, 912) -> [10000 ps] WR @ (1, 920) -> [10000 ps] WR @ (1, 928) -> [10000 ps] WR @ (1, 936) -> [10000 ps] WR @ (1, 944) -> -[10000 ps] WR @ (1, 952) -> [10000 ps] WR @ (1, 960) -> [10000 ps] WR @ (1, 968) -> [ 2500 ps] ACT @ (2, 16383) -> [ 7500 ps] WR @ (1, 976) -> -[10000 ps] WR @ (1, 984) -> [10000 ps] WR @ (1, 992) -> [10000 ps] WR @ (1, 1000) -> [10000 ps] WR @ (1, 1008) -> [10000 ps] WR @ (1, 1016) -> -[10000 ps] WR @ (2, 0) -> [10000 ps] WR @ (2, 8) -> [10000 ps] WR @ (2, 16) -> [10000 ps] WR @ (2, 24) -> [10000 ps] WR @ (2, 32) -> -[10000 ps] WR @ (2, 40) -> [10000 ps] WR @ (2, 48) -> [10000 ps] WR @ (2, 56) -> [10000 ps] WR @ (2, 64) -> [10000 ps] WR @ (2, 72) -> -[10000 ps] WR @ (2, 80) -> [10000 ps] WR @ (2, 88) -> [10000 ps] WR @ (2, 96) -> [10000 ps] WR @ (2, 104) -> [10000 ps] WR @ (2, 112) -> -[10000 ps] WR @ (2, 120) -> [10000 ps] WR @ (2, 128) -> [10000 ps] WR @ (2, 136) -> [10000 ps] WR @ (2, 144) -> [10000 ps] WR @ (2, 152) -> -[10000 ps] WR @ (2, 160) -> [10000 ps] WR @ (2, 168) -> [10000 ps] WR @ (2, 176) -> [10000 ps] WR @ (2, 184) -> [10000 ps] WR @ (2, 192) -> -[10000 ps] WR @ (2, 200) -> [10000 ps] WR @ (2, 208) -> [10000 ps] WR @ (2, 216) -> [10000 ps] WR @ (2, 224) -> [10000 ps] WR @ (2, 232) -> -[10000 ps] WR @ (2, 240) -> [10000 ps] WR @ (2, 248) -> [10000 ps] WR @ (2, 256) -> [10000 ps] WR @ (2, 264) -> [10000 ps] WR @ (2, 272) -> -[10000 ps] WR @ (2, 280) -> [10000 ps] WR @ (2, 288) -> [10000 ps] WR @ (2, 296) -> [10000 ps] WR @ (2, 304) -> [10000 ps] WR @ (2, 312) -> -[10000 ps] WR @ (2, 320) -> [10000 ps] WR @ (2, 328) -> [10000 ps] WR @ (2, 336) -> [10000 ps] WR @ (2, 344) -> [10000 ps] WR @ (2, 352) -> -[10000 ps] WR @ (2, 360) -> [10000 ps] WR @ (2, 368) -> [10000 ps] WR @ (2, 376) -> [10000 ps] WR @ (2, 384) -> [10000 ps] WR @ (2, 392) -> -[10000 ps] WR @ (2, 400) -> [10000 ps] WR @ (2, 408) -> [10000 ps] WR @ (2, 416) -> [10000 ps] WR @ (2, 424) -> [10000 ps] WR @ (2, 432) -> -[10000 ps] WR @ (2, 440) -> [10000 ps] WR @ (2, 448) -> [10000 ps] WR @ (2, 456) -> [10000 ps] WR @ (2, 464) -> [10000 ps] WR @ (2, 472) -> -[10000 ps] WR @ (2, 480) -> [10000 ps] WR @ (2, 488) -> [10000 ps] WR @ (2, 496) -> [10000 ps] WR @ (2, 504) -> [10000 ps] WR @ (2, 512) -> -[10000 ps] WR @ (2, 520) -> [10000 ps] WR @ (2, 528) -> [10000 ps] WR @ (2, 536) -> [10000 ps] WR @ (2, 544) -> [10000 ps] WR @ (2, 552) -> -[10000 ps] WR @ (2, 560) -> [10000 ps] WR @ (2, 568) -> [10000 ps] WR @ (2, 576) -> [10000 ps] WR @ (2, 584) -> [10000 ps] WR @ (2, 592) -> -[10000 ps] WR @ (2, 600) -> [10000 ps] WR @ (2, 608) -> [10000 ps] WR @ (2, 616) -> [10000 ps] WR @ (2, 624) -> [10000 ps] WR @ (2, 632) -> -[10000 ps] WR @ (2, 640) -> [10000 ps] WR @ (2, 648) -> [10000 ps] WR @ (2, 656) -> [10000 ps] WR @ (2, 664) -> [10000 ps] WR @ (2, 672) -> -[10000 ps] WR @ (2, 680) -> [10000 ps] WR @ (2, 688) -> [10000 ps] WR @ (2, 696) -> [10000 ps] WR @ (2, 704) -> [10000 ps] WR @ (2, 712) -> -[10000 ps] WR @ (2, 720) -> [10000 ps] WR @ (2, 728) -> [10000 ps] WR @ (2, 736) -> [10000 ps] WR @ (2, 744) -> [10000 ps] WR @ (2, 752) -> -[10000 ps] WR @ (2, 760) -> [10000 ps] WR @ (2, 768) -> [10000 ps] WR @ (2, 776) -> [10000 ps] WR @ (2, 784) -> [10000 ps] WR @ (2, 792) -> -[10000 ps] WR @ (2, 800) -> [10000 ps] WR @ (2, 808) -> [10000 ps] WR @ (2, 816) -> [10000 ps] WR @ (2, 824) -> [10000 ps] WR @ (2, 832) -> -[10000 ps] WR @ (2, 840) -> [10000 ps] WR @ (2, 848) -> [10000 ps] WR @ (2, 856) -> [10000 ps] WR @ (2, 864) -> [10000 ps] WR @ (2, 872) -> -[10000 ps] WR @ (2, 880) -> [10000 ps] WR @ (2, 888) -> [10000 ps] WR @ (2, 896) -> [10000 ps] WR @ (2, 904) -> [10000 ps] WR @ (2, 912) -> -[10000 ps] WR @ (2, 920) -> [10000 ps] WR @ (2, 928) -> [10000 ps] WR @ (2, 936) -> [10000 ps] WR @ (2, 944) -> [10000 ps] WR @ (2, 952) -> -[10000 ps] WR @ (2, 960) -> [10000 ps] WR @ (2, 968) -> [ 2500 ps] ACT @ (3, 16383) -> [ 7500 ps] WR @ (2, 976) -> [10000 ps] WR @ (2, 984) -> -[10000 ps] WR @ (2, 992) -> [10000 ps] WR @ (2, 1000) -> [10000 ps] WR @ (2, 1008) -> [10000 ps] WR @ (2, 1016) -> [10000 ps] WR @ (3, 0) -> -[10000 ps] WR @ (3, 8) -> [10000 ps] WR @ (3, 16) -> [10000 ps] WR @ (3, 24) -> [10000 ps] WR @ (3, 32) -> [10000 ps] WR @ (3, 40) -> -[10000 ps] WR @ (3, 48) -> [10000 ps] WR @ (3, 56) -> [10000 ps] WR @ (3, 64) -> [10000 ps] WR @ (3, 72) -> [10000 ps] WR @ (3, 80) -> -[10000 ps] WR @ (3, 88) -> [10000 ps] WR @ (3, 96) -> [10000 ps] WR @ (3, 104) -> [10000 ps] WR @ (3, 112) -> [10000 ps] WR @ (3, 120) -> -[10000 ps] WR @ (3, 128) -> [10000 ps] WR @ (3, 136) -> [10000 ps] WR @ (3, 144) -> [10000 ps] WR @ (3, 152) -> [10000 ps] WR @ (3, 160) -> -[10000 ps] WR @ (3, 168) -> [10000 ps] WR @ (3, 176) -> [10000 ps] WR @ (3, 184) -> [10000 ps] WR @ (3, 192) -> [10000 ps] WR @ (3, 200) -> -[10000 ps] WR @ (3, 208) -> [10000 ps] WR @ (3, 216) -> [10000 ps] WR @ (3, 224) -> [10000 ps] WR @ (3, 232) -> [10000 ps] WR @ (3, 240) -> -[10000 ps] WR @ (3, 248) -> [10000 ps] WR @ (3, 256) -> [10000 ps] WR @ (3, 264) -> [10000 ps] WR @ (3, 272) -> [10000 ps] WR @ (3, 280) -> -[10000 ps] WR @ (3, 288) -> [10000 ps] WR @ (3, 296) -> [10000 ps] WR @ (3, 304) -> [10000 ps] WR @ (3, 312) -> [10000 ps] WR @ (3, 320) -> -[10000 ps] WR @ (3, 328) -> [10000 ps] WR @ (3, 336) -> [10000 ps] WR @ (3, 344) -> [10000 ps] WR @ (3, 352) -> [10000 ps] WR @ (3, 360) -> -[10000 ps] WR @ (3, 368) -> [10000 ps] WR @ (3, 376) -> [10000 ps] WR @ (3, 384) -> [10000 ps] WR @ (3, 392) -> [10000 ps] WR @ (3, 400) -> -[10000 ps] WR @ (3, 408) -> [10000 ps] WR @ (3, 416) -> [10000 ps] WR @ (3, 424) -> [10000 ps] WR @ (3, 432) -> [10000 ps] WR @ (3, 440) -> -[10000 ps] WR @ (3, 448) -> [10000 ps] WR @ (3, 456) -> [10000 ps] WR @ (3, 464) -> [10000 ps] WR @ (3, 472) -> [10000 ps] WR @ (3, 480) -> -[10000 ps] WR @ (3, 488) -> [10000 ps] WR @ (3, 496) -> [10000 ps] WR @ (3, 504) -> [10000 ps] WR @ (3, 512) -> [10000 ps] WR @ (3, 520) -> -[10000 ps] WR @ (3, 528) -> [10000 ps] WR @ (3, 536) -> [10000 ps] WR @ (3, 544) -> [10000 ps] WR @ (3, 552) -> [10000 ps] WR @ (3, 560) -> -[10000 ps] WR @ (3, 568) -> [10000 ps] WR @ (3, 576) -> [10000 ps] WR @ (3, 584) -> [10000 ps] WR @ (3, 592) -> [10000 ps] WR @ (3, 600) -> -[10000 ps] WR @ (3, 608) -> [10000 ps] WR @ (3, 616) -> [10000 ps] WR @ (3, 624) -> [10000 ps] WR @ (3, 632) -> [10000 ps] WR @ (3, 640) -> -[10000 ps] WR @ (3, 648) -> [10000 ps] WR @ (3, 656) -> [10000 ps] WR @ (3, 664) -> [10000 ps] WR @ (3, 672) -> [10000 ps] WR @ (3, 680) -> -[10000 ps] WR @ (3, 688) -> [10000 ps] WR @ (3, 696) -> [10000 ps] WR @ (3, 704) -> [10000 ps] WR @ (3, 712) -> [10000 ps] WR @ (3, 720) -> -[10000 ps] WR @ (3, 728) -> [10000 ps] WR @ (3, 736) -> [10000 ps] WR @ (3, 744) -> [10000 ps] WR @ (3, 752) -> [10000 ps] WR @ (3, 760) -> -[10000 ps] WR @ (3, 768) -> [10000 ps] WR @ (3, 776) -> [10000 ps] WR @ (3, 784) -> [10000 ps] WR @ (3, 792) -> [10000 ps] WR @ (3, 800) -> -[10000 ps] WR @ (3, 808) -> [10000 ps] WR @ (3, 816) -> [10000 ps] WR @ (3, 824) -> [10000 ps] WR @ (3, 832) -> [10000 ps] WR @ (3, 840) -> -[10000 ps] WR @ (3, 848) -> [10000 ps] WR @ (3, 856) -> [10000 ps] WR @ (3, 864) -> [10000 ps] WR @ (3, 872) -> [10000 ps] WR @ (3, 880) -> -[10000 ps] WR @ (3, 888) -> [10000 ps] WR @ (3, 896) -> [10000 ps] WR @ (3, 904) -> [10000 ps] WR @ (3, 912) -> [10000 ps] WR @ (3, 920) -> -[10000 ps] WR @ (3, 928) -> [10000 ps] WR @ (3, 936) -> [10000 ps] WR @ (3, 944) -> [10000 ps] WR @ (3, 952) -> [10000 ps] WR @ (3, 960) -> -[10000 ps] WR @ (3, 968) -> [ 2500 ps] ACT @ (4, 16383) -> [ 7500 ps] WR @ (3, 976) -> [10000 ps] WR @ (3, 984) -> [10000 ps] WR @ (3, 992) -> -[10000 ps] WR @ (3, 1000) -> [10000 ps] WR @ (3, 1008) -> [10000 ps] WR @ (3, 1016) -> [10000 ps] WR @ (4, 0) -> [10000 ps] WR @ (4, 8) -> -[10000 ps] WR @ (4, 16) -> [10000 ps] WR @ (4, 24) -> [10000 ps] WR @ (4, 32) -> [10000 ps] WR @ (4, 40) -> [10000 ps] WR @ (4, 48) -> -[10000 ps] WR @ (4, 56) -> [10000 ps] WR @ (4, 64) -> [10000 ps] WR @ (4, 72) -> [10000 ps] WR @ (4, 80) -> [10000 ps] WR @ (4, 88) -> -[10000 ps] WR @ (4, 96) -> [10000 ps] WR @ (4, 104) -> [10000 ps] WR @ (4, 112) -> [10000 ps] WR @ (4, 120) -> [10000 ps] WR @ (4, 128) -> -[10000 ps] WR @ (4, 136) -> [10000 ps] WR @ (4, 144) -> [10000 ps] WR @ (4, 152) -> [10000 ps] WR @ (4, 160) -> [10000 ps] WR @ (4, 168) -> -[10000 ps] WR @ (4, 176) -> [10000 ps] WR @ (4, 184) -> [10000 ps] WR @ (4, 192) -> [10000 ps] WR @ (4, 200) -> [10000 ps] WR @ (4, 208) -> -[10000 ps] WR @ (4, 216) -> [10000 ps] WR @ (4, 224) -> [10000 ps] WR @ (4, 232) -> [10000 ps] WR @ (4, 240) -> [10000 ps] WR @ (4, 248) -> -[10000 ps] WR @ (4, 256) -> [10000 ps] WR @ (4, 264) -> [10000 ps] WR @ (4, 272) -> [10000 ps] WR @ (4, 280) -> [10000 ps] WR @ (4, 288) -> -[10000 ps] WR @ (4, 296) -> [10000 ps] WR @ (4, 304) -> [10000 ps] WR @ (4, 312) -> [10000 ps] WR @ (4, 320) -> [10000 ps] WR @ (4, 328) -> -[10000 ps] WR @ (4, 336) -> [10000 ps] WR @ (4, 344) -> [10000 ps] WR @ (4, 352) -> [10000 ps] WR @ (4, 360) -> [10000 ps] WR @ (4, 368) -> -[10000 ps] WR @ (4, 376) -> [10000 ps] WR @ (4, 384) -> [10000 ps] WR @ (4, 392) -> [10000 ps] WR @ (4, 400) -> [10000 ps] WR @ (4, 408) -> -[10000 ps] WR @ (4, 416) -> [10000 ps] WR @ (4, 424) -> [10000 ps] WR @ (4, 432) -> [10000 ps] WR @ (4, 440) -> [10000 ps] WR @ (4, 448) -> -[10000 ps] WR @ (4, 456) -> [10000 ps] WR @ (4, 464) -> [10000 ps] WR @ (4, 472) -> [10000 ps] WR @ (4, 480) -> [10000 ps] WR @ (4, 488) -> -[10000 ps] WR @ (4, 496) -> [10000 ps] WR @ (4, 504) -> [10000 ps] WR @ (4, 512) -> [10000 ps] WR @ (4, 520) -> [10000 ps] WR @ (4, 528) -> -[10000 ps] WR @ (4, 536) -> [10000 ps] WR @ (4, 544) -> [10000 ps] WR @ (4, 552) -> [10000 ps] WR @ (4, 560) -> [10000 ps] WR @ (4, 568) -> -[10000 ps] WR @ (4, 576) -> [10000 ps] WR @ (4, 584) -> [10000 ps] WR @ (4, 592) -> [10000 ps] WR @ (4, 600) -> [10000 ps] WR @ (4, 608) -> -[10000 ps] WR @ (4, 616) -> [10000 ps] WR @ (4, 624) -> [10000 ps] WR @ (4, 632) -> [10000 ps] WR @ (4, 640) -> [10000 ps] WR @ (4, 648) -> -[10000 ps] WR @ (4, 656) -> [10000 ps] WR @ (4, 664) -> [10000 ps] WR @ (4, 672) -> [10000 ps] WR @ (4, 680) -> [10000 ps] WR @ (4, 688) -> -[10000 ps] WR @ (4, 696) -> [10000 ps] WR @ (4, 704) -> [10000 ps] WR @ (4, 712) -> [10000 ps] WR @ (4, 720) -> [10000 ps] WR @ (4, 728) -> -[10000 ps] WR @ (4, 736) -> [10000 ps] WR @ (4, 744) -> [10000 ps] WR @ (4, 752) -> [10000 ps] WR @ (4, 760) -> [10000 ps] WR @ (4, 768) -> -[10000 ps] WR @ (4, 776) -> [10000 ps] WR @ (4, 784) -> [10000 ps] WR @ (4, 792) -> [10000 ps] WR @ (4, 800) -> [10000 ps] WR @ (4, 808) -> -[10000 ps] WR @ (4, 816) -> [10000 ps] WR @ (4, 824) -> [10000 ps] WR @ (4, 832) -> [10000 ps] WR @ (4, 840) -> [10000 ps] WR @ (4, 848) -> -[10000 ps] WR @ (4, 856) -> [10000 ps] WR @ (4, 864) -> [10000 ps] WR @ (4, 872) -> [10000 ps] WR @ (4, 880) -> [10000 ps] WR @ (4, 888) -> -[10000 ps] WR @ (4, 896) -> [10000 ps] WR @ (4, 904) -> [10000 ps] WR @ (4, 912) -> [10000 ps] WR @ (4, 920) -> [10000 ps] WR @ (4, 928) -> -[10000 ps] WR @ (4, 936) -> [10000 ps] WR @ (4, 944) -> [10000 ps] WR @ (4, 952) -> [10000 ps] WR @ (4, 960) -> [10000 ps] WR @ (4, 968) -> -[ 2500 ps] ACT @ (5, 16383) -> [ 7500 ps] WR @ (4, 976) -> [10000 ps] WR @ (4, 984) -> [10000 ps] WR @ (4, 992) -> [10000 ps] WR @ (4, 1000) -> -[10000 ps] WR @ (4, 1008) -> [10000 ps] WR @ (4, 1016) -> [10000 ps] WR @ (5, 0) -> [10000 ps] WR @ (5, 8) -> [10000 ps] WR @ (5, 16) -> -[10000 ps] WR @ (5, 24) -> [10000 ps] WR @ (5, 32) -> [10000 ps] WR @ (5, 40) -> [10000 ps] WR @ (5, 48) -> [10000 ps] WR @ (5, 56) -> -[10000 ps] WR @ (5, 64) -> [10000 ps] WR @ (5, 72) -> [10000 ps] WR @ (5, 80) -> [10000 ps] WR @ (5, 88) -> [10000 ps] WR @ (5, 96) -> -[10000 ps] WR @ (5, 104) -> [10000 ps] WR @ (5, 112) -> [10000 ps] WR @ (5, 120) -> [10000 ps] WR @ (5, 128) -> [10000 ps] WR @ (5, 136) -> -[10000 ps] WR @ (5, 144) -> [10000 ps] WR @ (5, 152) -> [10000 ps] WR @ (5, 160) -> [10000 ps] WR @ (5, 168) -> [10000 ps] WR @ (5, 176) -> -[10000 ps] WR @ (5, 184) -> [10000 ps] WR @ (5, 192) -> [10000 ps] WR @ (5, 200) -> [10000 ps] WR @ (5, 208) -> [10000 ps] WR @ (5, 216) -> -[10000 ps] WR @ (5, 224) -> [10000 ps] WR @ (5, 232) -> [10000 ps] WR @ (5, 240) -> [10000 ps] WR @ (5, 248) -> [10000 ps] WR @ (5, 256) -> -[10000 ps] WR @ (5, 264) -> [10000 ps] WR @ (5, 272) -> [10000 ps] WR @ (5, 280) -> [10000 ps] WR @ (5, 288) -> [10000 ps] WR @ (5, 296) -> -[10000 ps] WR @ (5, 304) -> [10000 ps] WR @ (5, 312) -> [10000 ps] WR @ (5, 320) -> [10000 ps] WR @ (5, 328) -> [10000 ps] WR @ (5, 336) -> -[10000 ps] WR @ (5, 344) -> [10000 ps] WR @ (5, 352) -> [10000 ps] WR @ (5, 360) -> [10000 ps] WR @ (5, 368) -> [10000 ps] WR @ (5, 376) -> -[10000 ps] WR @ (5, 384) -> [10000 ps] WR @ (5, 392) -> [10000 ps] WR @ (5, 400) -> [10000 ps] WR @ (5, 408) -> [10000 ps] WR @ (5, 416) -> -[10000 ps] WR @ (5, 424) -> [10000 ps] WR @ (5, 432) -> [10000 ps] WR @ (5, 440) -> [10000 ps] WR @ (5, 448) -> [10000 ps] WR @ (5, 456) -> -[10000 ps] WR @ (5, 464) -> [10000 ps] WR @ (5, 472) -> [10000 ps] WR @ (5, 480) -> [10000 ps] WR @ (5, 488) -> [10000 ps] WR @ (5, 496) -> -[10000 ps] WR @ (5, 504) -> [10000 ps] WR @ (5, 512) -> [10000 ps] WR @ (5, 520) -> [10000 ps] WR @ (5, 528) -> [10000 ps] WR @ (5, 536) -> -[10000 ps] WR @ (5, 544) -> [10000 ps] WR @ (5, 552) -> [10000 ps] WR @ (5, 560) -> [10000 ps] WR @ (5, 568) -> [10000 ps] WR @ (5, 576) -> -[10000 ps] WR @ (5, 584) -> [10000 ps] WR @ (5, 592) -> [10000 ps] WR @ (5, 600) -> [10000 ps] WR @ (5, 608) -> [10000 ps] WR @ (5, 616) -> -[10000 ps] WR @ (5, 624) -> [10000 ps] WR @ (5, 632) -> [10000 ps] WR @ (5, 640) -> [10000 ps] WR @ (5, 648) -> [10000 ps] WR @ (5, 656) -> -[10000 ps] WR @ (5, 664) -> [10000 ps] WR @ (5, 672) -> [10000 ps] WR @ (5, 680) -> [10000 ps] WR @ (5, 688) -> [10000 ps] WR @ (5, 696) -> -[10000 ps] WR @ (5, 704) -> [10000 ps] WR @ (5, 712) -> [10000 ps] WR @ (5, 720) -> [10000 ps] WR @ (5, 728) -> [10000 ps] WR @ (5, 736) -> -[10000 ps] WR @ (5, 744) -> [10000 ps] WR @ (5, 752) -> [10000 ps] WR @ (5, 760) -> [10000 ps] WR @ (5, 768) -> [10000 ps] WR @ (5, 776) -> -[10000 ps] WR @ (5, 784) -> [10000 ps] WR @ (5, 792) -> [10000 ps] WR @ (5, 800) -> [10000 ps] WR @ (5, 808) -> [10000 ps] WR @ (5, 816) -> -[10000 ps] WR @ (5, 824) -> [10000 ps] WR @ (5, 832) -> [10000 ps] WR @ (5, 840) -> [10000 ps] WR @ (5, 848) -> [10000 ps] WR @ (5, 856) -> -[10000 ps] WR @ (5, 864) -> [10000 ps] WR @ (5, 872) -> [10000 ps] WR @ (5, 880) -> [10000 ps] WR @ (5, 888) -> [10000 ps] WR @ (5, 896) -> -[10000 ps] WR @ (5, 904) -> [10000 ps] WR @ (5, 912) -> [10000 ps] WR @ (5, 920) -> [10000 ps] WR @ (5, 928) -> [10000 ps] WR @ (5, 936) -> -[10000 ps] WR @ (5, 944) -> [10000 ps] WR @ (5, 952) -> [10000 ps] WR @ (5, 960) -> [10000 ps] WR @ (5, 968) -> [ 2500 ps] ACT @ (6, 16383) -> -[ 7500 ps] WR @ (5, 976) -> [10000 ps] WR @ (5, 984) -> [10000 ps] WR @ (5, 992) -> [10000 ps] WR @ (5, 1000) -> [10000 ps] WR @ (5, 1008) -> -[10000 ps] WR @ (5, 1016) -> [10000 ps] WR @ (6, 0) -> [10000 ps] WR @ (6, 8) -> [10000 ps] WR @ (6, 16) -> [10000 ps] WR @ (6, 24) -> -[10000 ps] WR @ (6, 32) -> [10000 ps] WR @ (6, 40) -> [10000 ps] WR @ (6, 48) -> [10000 ps] WR @ (6, 56) -> [10000 ps] WR @ (6, 64) -> -[10000 ps] WR @ (6, 72) -> [10000 ps] WR @ (6, 80) -> [10000 ps] WR @ (6, 88) -> [10000 ps] WR @ (6, 96) -> [10000 ps] WR @ (6, 104) -> -[10000 ps] WR @ (6, 112) -> [10000 ps] WR @ (6, 120) -> [10000 ps] WR @ (6, 128) -> [10000 ps] WR @ (6, 136) -> [10000 ps] WR @ (6, 144) -> -[10000 ps] WR @ (6, 152) -> [10000 ps] WR @ (6, 160) -> [10000 ps] WR @ (6, 168) -> [10000 ps] WR @ (6, 176) -> [10000 ps] WR @ (6, 184) -> -[10000 ps] WR @ (6, 192) -> [10000 ps] WR @ (6, 200) -> [10000 ps] WR @ (6, 208) -> [10000 ps] WR @ (6, 216) -> [10000 ps] WR @ (6, 224) -> -[ 5000 ps] NOP -> [ 5000 ps] WR @ (6, 232) -> [10000 ps] WR @ (6, 240) -> [10000 ps] WR @ (6, 248) -> [65000 ps] PRE @ (0) -> -[30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (6, 16383) -> [17500 ps] WR @ (6, 256) -> [10000 ps] WR @ (6, 264) -> -[10000 ps] WR @ (6, 272) -> [10000 ps] WR @ (6, 280) -> [10000 ps] WR @ (6, 288) -> [10000 ps] WR @ (6, 296) -> [10000 ps] WR @ (6, 304) -> -[10000 ps] WR @ (6, 312) -> [10000 ps] WR @ (6, 320) -> [10000 ps] WR @ (6, 328) -> [10000 ps] WR @ (6, 336) -> [10000 ps] WR @ (6, 344) -> -[10000 ps] WR @ (6, 352) -> [10000 ps] WR @ (6, 360) -> [10000 ps] WR @ (6, 368) -> [10000 ps] WR @ (6, 376) -> [10000 ps] WR @ (6, 384) -> -[10000 ps] WR @ (6, 392) -> [10000 ps] WR @ (6, 400) -> [10000 ps] WR @ (6, 408) -> [10000 ps] WR @ (6, 416) -> [10000 ps] WR @ (6, 424) -> -[10000 ps] WR @ (6, 432) -> [10000 ps] WR @ (6, 440) -> [10000 ps] WR @ (6, 448) -> [10000 ps] WR @ (6, 456) -> [10000 ps] WR @ (6, 464) -> -[10000 ps] WR @ (6, 472) -> [10000 ps] WR @ (6, 480) -> [10000 ps] WR @ (6, 488) -> [10000 ps] WR @ (6, 496) -> [10000 ps] WR @ (6, 504) -> -[10000 ps] WR @ (6, 512) -> [10000 ps] WR @ (6, 520) -> [10000 ps] WR @ (6, 528) -> [10000 ps] WR @ (6, 536) -> [10000 ps] WR @ (6, 544) -> -[10000 ps] WR @ (6, 552) -> [10000 ps] WR @ (6, 560) -> [10000 ps] WR @ (6, 568) -> [10000 ps] WR @ (6, 576) -> [10000 ps] WR @ (6, 584) -> -[10000 ps] WR @ (6, 592) -> [10000 ps] WR @ (6, 600) -> [10000 ps] WR @ (6, 608) -> [10000 ps] WR @ (6, 616) -> [10000 ps] WR @ (6, 624) -> -[10000 ps] WR @ (6, 632) -> [10000 ps] WR @ (6, 640) -> [10000 ps] WR @ (6, 648) -> [10000 ps] WR @ (6, 656) -> [10000 ps] WR @ (6, 664) -> -[10000 ps] WR @ (6, 672) -> [10000 ps] WR @ (6, 680) -> [10000 ps] WR @ (6, 688) -> [10000 ps] WR @ (6, 696) -> [10000 ps] WR @ (6, 704) -> -[10000 ps] WR @ (6, 712) -> [10000 ps] WR @ (6, 720) -> [10000 ps] WR @ (6, 728) -> [10000 ps] WR @ (6, 736) -> [10000 ps] WR @ (6, 744) -> -[10000 ps] WR @ (6, 752) -> [10000 ps] WR @ (6, 760) -> [10000 ps] WR @ (6, 768) -> [10000 ps] WR @ (6, 776) -> [10000 ps] WR @ (6, 784) -> -[10000 ps] WR @ (6, 792) -> [10000 ps] WR @ (6, 800) -> [10000 ps] WR @ (6, 808) -> [10000 ps] WR @ (6, 816) -> [10000 ps] WR @ (6, 824) -> -[10000 ps] WR @ (6, 832) -> [10000 ps] WR @ (6, 840) -> [10000 ps] WR @ (6, 848) -> [10000 ps] WR @ (6, 856) -> [10000 ps] WR @ (6, 864) -> -[10000 ps] WR @ (6, 872) -> [10000 ps] WR @ (6, 880) -> [10000 ps] WR @ (6, 888) -> [10000 ps] WR @ (6, 896) -> [10000 ps] WR @ (6, 904) -> -[10000 ps] WR @ (6, 912) -> [10000 ps] WR @ (6, 920) -> [10000 ps] WR @ (6, 928) -> [10000 ps] WR @ (6, 936) -> [10000 ps] WR @ (6, 944) -> -[10000 ps] WR @ (6, 952) -> [10000 ps] WR @ (6, 960) -> [10000 ps] WR @ (6, 968) -> [ 2500 ps] ACT @ (7, 16383) -> [ 7500 ps] WR @ (6, 976) -> -[10000 ps] WR @ (6, 984) -> [10000 ps] WR @ (6, 992) -> [10000 ps] WR @ (6, 1000) -> [10000 ps] WR @ (6, 1008) -> [10000 ps] WR @ (6, 1016) -> -[10000 ps] WR @ (7, 0) -> [10000 ps] WR @ (7, 8) -> [10000 ps] WR @ (7, 16) -> [10000 ps] WR @ (7, 24) -> [10000 ps] WR @ (7, 32) -> -[10000 ps] WR @ (7, 40) -> [10000 ps] WR @ (7, 48) -> [10000 ps] WR @ (7, 56) -> [10000 ps] WR @ (7, 64) -> [10000 ps] WR @ (7, 72) -> -[10000 ps] WR @ (7, 80) -> [10000 ps] WR @ (7, 88) -> [10000 ps] WR @ (7, 96) -> [10000 ps] WR @ (7, 104) -> [10000 ps] WR @ (7, 112) -> -[10000 ps] WR @ (7, 120) -> [10000 ps] WR @ (7, 128) -> [10000 ps] WR @ (7, 136) -> [10000 ps] WR @ (7, 144) -> [10000 ps] WR @ (7, 152) -> -[10000 ps] WR @ (7, 160) -> [10000 ps] WR @ (7, 168) -> [10000 ps] WR @ (7, 176) -> [10000 ps] WR @ (7, 184) -> [10000 ps] WR @ (7, 192) -> -[10000 ps] WR @ (7, 200) -> [10000 ps] WR @ (7, 208) -> [10000 ps] WR @ (7, 216) -> [10000 ps] WR @ (7, 224) -> [10000 ps] WR @ (7, 232) -> -[10000 ps] WR @ (7, 240) -> [10000 ps] WR @ (7, 248) -> [10000 ps] WR @ (7, 256) -> [10000 ps] WR @ (7, 264) -> [10000 ps] WR @ (7, 272) -> -[10000 ps] WR @ (7, 280) -> [10000 ps] WR @ (7, 288) -> [10000 ps] WR @ (7, 296) -> [10000 ps] WR @ (7, 304) -> [10000 ps] WR @ (7, 312) -> -[10000 ps] WR @ (7, 320) -> [10000 ps] WR @ (7, 328) -> [10000 ps] WR @ (7, 336) -> [10000 ps] WR @ (7, 344) -> [10000 ps] WR @ (7, 352) -> -[10000 ps] WR @ (7, 360) -> [10000 ps] WR @ (7, 368) -> [10000 ps] WR @ (7, 376) -> [10000 ps] WR @ (7, 384) -> [10000 ps] WR @ (7, 392) -> -[10000 ps] WR @ (7, 400) -> [10000 ps] WR @ (7, 408) -> [10000 ps] WR @ (7, 416) -> [10000 ps] WR @ (7, 424) -> [10000 ps] WR @ (7, 432) -> -[10000 ps] WR @ (7, 440) -> [10000 ps] WR @ (7, 448) -> [10000 ps] WR @ (7, 456) -> [10000 ps] WR @ (7, 464) -> [10000 ps] WR @ (7, 472) -> -[10000 ps] WR @ (7, 480) -> [10000 ps] WR @ (7, 488) -> [10000 ps] WR @ (7, 496) -> [10000 ps] WR @ (7, 504) -> [10000 ps] WR @ (7, 512) -> -[10000 ps] WR @ (7, 520) -> [10000 ps] WR @ (7, 528) -> [10000 ps] WR @ (7, 536) -> [10000 ps] WR @ (7, 544) -> [10000 ps] WR @ (7, 552) -> -[10000 ps] WR @ (7, 560) -> [10000 ps] WR @ (7, 568) -> [10000 ps] WR @ (7, 576) -> [10000 ps] WR @ (7, 584) -> [10000 ps] WR @ (7, 592) -> -[10000 ps] WR @ (7, 600) -> [10000 ps] WR @ (7, 608) -> [10000 ps] WR @ (7, 616) -> [10000 ps] WR @ (7, 624) -> [10000 ps] WR @ (7, 632) -> -[10000 ps] WR @ (7, 640) -> [10000 ps] WR @ (7, 648) -> [10000 ps] WR @ (7, 656) -> [10000 ps] WR @ (7, 664) -> [10000 ps] WR @ (7, 672) -> -[10000 ps] WR @ (7, 680) -> [10000 ps] WR @ (7, 688) -> [10000 ps] WR @ (7, 696) -> [10000 ps] WR @ (7, 704) -> [10000 ps] WR @ (7, 712) -> -[10000 ps] WR @ (7, 720) -> [10000 ps] WR @ (7, 728) -> [10000 ps] WR @ (7, 736) -> [10000 ps] WR @ (7, 744) -> [10000 ps] WR @ (7, 752) -> -[10000 ps] WR @ (7, 760) -> [10000 ps] WR @ (7, 768) -> [10000 ps] WR @ (7, 776) -> [10000 ps] WR @ (7, 784) -> [10000 ps] WR @ (7, 792) -> -[10000 ps] WR @ (7, 800) -> [10000 ps] WR @ (7, 808) -> [10000 ps] WR @ (7, 816) -> [10000 ps] WR @ (7, 824) -> [10000 ps] WR @ (7, 832) -> -[10000 ps] WR @ (7, 840) -> [10000 ps] WR @ (7, 848) -> [10000 ps] WR @ (7, 856) -> [10000 ps] WR @ (7, 864) -> [10000 ps] WR @ (7, 872) -> -[10000 ps] WR @ (7, 880) -> [10000 ps] WR @ (7, 888) -> [10000 ps] WR @ (7, 896) -> [10000 ps] WR @ (7, 904) -> [10000 ps] WR @ (7, 912) -> -[10000 ps] WR @ (7, 920) -> [10000 ps] WR @ (7, 928) -> [10000 ps] WR @ (7, 936) -> [10000 ps] WR @ (7, 944) -> [10000 ps] WR @ (7, 952) -> -[10000 ps] WR @ (7, 960) -> [10000 ps] WR @ (7, 968) -> [ 2500 ps] ACT @ (0, 0) -> [ 7500 ps] WR @ (7, 976) -> [10000 ps] WR @ (7, 984) -> -[10000 ps] WR @ (7, 992) -> [10000 ps] WR @ (7, 1000) -> [10000 ps] WR @ (7, 1008) -> [10000 ps] WR @ (7, 1016) -> [10000 ps] WR @ (0, 0) -> -[10000 ps] WR @ (0, 8) -> [10000 ps] WR @ (0, 16) -> [10000 ps] WR @ (0, 24) -> [10000 ps] WR @ (0, 32) -> [10000 ps] WR @ (0, 40) -> -[10000 ps] WR @ (0, 48) -> [10000 ps] WR @ (0, 56) -> [10000 ps] WR @ (0, 64) -> [10000 ps] WR @ (0, 72) -> [10000 ps] WR @ (0, 80) -> -[10000 ps] WR @ (0, 88) -> [10000 ps] WR @ (0, 96) -> [10000 ps] WR @ (0, 104) -> [10000 ps] WR @ (0, 112) -> [10000 ps] WR @ (0, 120) -> -[10000 ps] WR @ (0, 128) -> [10000 ps] WR @ (0, 136) -> [10000 ps] WR @ (0, 144) -> [10000 ps] WR @ (0, 152) -> [10000 ps] WR @ (0, 160) -> -[10000 ps] WR @ (0, 168) -> [10000 ps] WR @ (0, 176) -> [10000 ps] WR @ (0, 184) -> [10000 ps] WR @ (0, 192) -> [10000 ps] WR @ (0, 200) -> -[10000 ps] WR @ (0, 208) -> [10000 ps] WR @ (0, 216) -> [10000 ps] WR @ (0, 224) -> [10000 ps] WR @ (0, 232) -> [10000 ps] WR @ (0, 240) -> -[10000 ps] WR @ (0, 248) -> [10000 ps] WR @ (0, 256) -> [10000 ps] WR @ (0, 264) -> [10000 ps] WR @ (0, 272) -> [10000 ps] WR @ (0, 280) -> -[10000 ps] WR @ (0, 288) -> [10000 ps] WR @ (0, 296) -> [10000 ps] WR @ (0, 304) -> [10000 ps] WR @ (0, 312) -> [10000 ps] WR @ (0, 320) -> -[10000 ps] WR @ (0, 328) -> [10000 ps] WR @ (0, 336) -> [10000 ps] WR @ (0, 344) -> [10000 ps] WR @ (0, 352) -> [10000 ps] WR @ (0, 360) -> -[10000 ps] WR @ (0, 368) -> [10000 ps] WR @ (0, 376) -> [10000 ps] WR @ (0, 384) -> [10000 ps] WR @ (0, 392) -> [10000 ps] WR @ (0, 400) -> -[10000 ps] WR @ (0, 408) -> [10000 ps] WR @ (0, 416) -> [10000 ps] WR @ (0, 424) -> [10000 ps] WR @ (0, 432) -> [10000 ps] WR @ (0, 440) -> -[10000 ps] WR @ (0, 448) -> [10000 ps] WR @ (0, 456) -> [10000 ps] WR @ (0, 464) -> [10000 ps] WR @ (0, 472) -> [10000 ps] WR @ (0, 480) -> -[10000 ps] WR @ (0, 488) -> [10000 ps] WR @ (0, 496) -> [10000 ps] WR @ (0, 504) -> [10000 ps] WR @ (0, 512) -> [10000 ps] WR @ (0, 520) -> -[10000 ps] WR @ (0, 528) -> [10000 ps] WR @ (0, 536) -> [10000 ps] WR @ (0, 544) -> [10000 ps] WR @ (0, 552) -> [10000 ps] WR @ (0, 560) -> -[10000 ps] WR @ (0, 568) -> [10000 ps] WR @ (0, 576) -> [10000 ps] WR @ (0, 584) -> [10000 ps] WR @ (0, 592) -> [10000 ps] WR @ (0, 600) -> -[10000 ps] WR @ (0, 608) -> [10000 ps] WR @ (0, 616) -> [10000 ps] WR @ (0, 624) -> [10000 ps] WR @ (0, 632) -> [10000 ps] WR @ (0, 640) -> -[10000 ps] WR @ (0, 648) -> [10000 ps] WR @ (0, 656) -> [10000 ps] WR @ (0, 664) -> [10000 ps] WR @ (0, 672) -> [10000 ps] WR @ (0, 680) -> -[10000 ps] WR @ (0, 688) -> [10000 ps] WR @ (0, 696) -> [10000 ps] WR @ (0, 704) -> [10000 ps] WR @ (0, 712) -> [10000 ps] WR @ (0, 720) -> -[10000 ps] WR @ (0, 728) -> [10000 ps] WR @ (0, 736) -> [10000 ps] WR @ (0, 744) -> [10000 ps] WR @ (0, 752) -> [10000 ps] WR @ (0, 760) -> -[10000 ps] WR @ (0, 768) -> [10000 ps] WR @ (0, 776) -> [10000 ps] WR @ (0, 784) -> [10000 ps] WR @ (0, 792) -> [10000 ps] WR @ (0, 800) -> -[10000 ps] WR @ (0, 808) -> [10000 ps] WR @ (0, 816) -> [10000 ps] WR @ (0, 824) -> [10000 ps] WR @ (0, 832) -> [10000 ps] WR @ (0, 840) -> -[10000 ps] WR @ (0, 848) -> [10000 ps] WR @ (0, 856) -> [10000 ps] WR @ (0, 864) -> [10000 ps] WR @ (0, 872) -> [10000 ps] WR @ (0, 880) -> -[10000 ps] WR @ (0, 888) -> [10000 ps] WR @ (0, 896) -> [10000 ps] WR @ (0, 904) -> [10000 ps] WR @ (0, 912) -> [10000 ps] WR @ (0, 920) -> -[10000 ps] WR @ (0, 928) -> [10000 ps] WR @ (0, 936) -> [10000 ps] WR @ (0, 944) -> [10000 ps] WR @ (0, 952) -> [10000 ps] WR @ (0, 960) -> -[10000 ps] WR @ (0, 968) -> [ 2500 ps] ACT @ (1, 0) -> [ 7500 ps] WR @ (0, 976) -> [10000 ps] WR @ (0, 984) -> [10000 ps] WR @ (0, 992) -> -[10000 ps] WR @ (0, 1000) -> [10000 ps] WR @ (0, 1008) -> [10000 ps] WR @ (0, 1016) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16383) -> -[15000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> [10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> [10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> [10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> -[10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> [10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> -[10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> [10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> -[10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> [10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> -[10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> [10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> -[10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> [10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> [10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> [10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> -[10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> [10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> [10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> [10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> -[10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> [10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> -[10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> [10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> -[10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> [10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> -[10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> [10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> -[10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> [10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> [10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> [10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> -[10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> [10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> -[10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> [10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> [10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> -[10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> [10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> -[10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> [ 7500 ps] PRE @ (1) -> [ 2500 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> -[ 5000 ps] ACT @ (1, 16383) -> [ 5000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> [10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> -[10000 ps] RD @ (1, 0) -> [10000 ps] RD @ (1, 8) -> [10000 ps] RD @ (1, 16) -> [10000 ps] RD @ (1, 24) -> [10000 ps] RD @ (1, 32) -> -[10000 ps] RD @ (1, 40) -> [10000 ps] RD @ (1, 48) -> [10000 ps] RD @ (1, 56) -> [10000 ps] RD @ (1, 64) -> [10000 ps] RD @ (1, 72) -> -[10000 ps] RD @ (1, 80) -> [10000 ps] RD @ (1, 88) -> [10000 ps] RD @ (1, 96) -> [10000 ps] RD @ (1, 104) -> [10000 ps] RD @ (1, 112) -> -[10000 ps] RD @ (1, 120) -> [10000 ps] RD @ (1, 128) -> [10000 ps] RD @ (1, 136) -> [10000 ps] RD @ (1, 144) -> [10000 ps] RD @ (1, 152) -> -[10000 ps] RD @ (1, 160) -> [10000 ps] RD @ (1, 168) -> [10000 ps] RD @ (1, 176) -> [10000 ps] RD @ (1, 184) -> [10000 ps] RD @ (1, 192) -> -[10000 ps] RD @ (1, 200) -> [10000 ps] RD @ (1, 208) -> [10000 ps] RD @ (1, 216) -> [10000 ps] RD @ (1, 224) -> [10000 ps] RD @ (1, 232) -> -[10000 ps] RD @ (1, 240) -> [10000 ps] RD @ (1, 248) -> [10000 ps] RD @ (1, 256) -> [10000 ps] RD @ (1, 264) -> [10000 ps] RD @ (1, 272) -> -[10000 ps] RD @ (1, 280) -> [10000 ps] RD @ (1, 288) -> [10000 ps] RD @ (1, 296) -> [10000 ps] RD @ (1, 304) -> [10000 ps] RD @ (1, 312) -> -[10000 ps] RD @ (1, 320) -> [10000 ps] RD @ (1, 328) -> [10000 ps] RD @ (1, 336) -> [10000 ps] RD @ (1, 344) -> [10000 ps] RD @ (1, 352) -> -[10000 ps] RD @ (1, 360) -> [10000 ps] RD @ (1, 368) -> [10000 ps] RD @ (1, 376) -> [10000 ps] RD @ (1, 384) -> [10000 ps] RD @ (1, 392) -> -[10000 ps] RD @ (1, 400) -> [10000 ps] RD @ (1, 408) -> [10000 ps] RD @ (1, 416) -> [10000 ps] RD @ (1, 424) -> [10000 ps] RD @ (1, 432) -> -[10000 ps] RD @ (1, 440) -> [10000 ps] RD @ (1, 448) -> [10000 ps] RD @ (1, 456) -> [10000 ps] RD @ (1, 464) -> [10000 ps] RD @ (1, 472) -> -[10000 ps] RD @ (1, 480) -> [10000 ps] RD @ (1, 488) -> [10000 ps] RD @ (1, 496) -> [10000 ps] RD @ (1, 504) -> [10000 ps] RD @ (1, 512) -> -[10000 ps] RD @ (1, 520) -> [10000 ps] RD @ (1, 528) -> [10000 ps] RD @ (1, 536) -> [10000 ps] RD @ (1, 544) -> [10000 ps] RD @ (1, 552) -> -[10000 ps] RD @ (1, 560) -> [10000 ps] RD @ (1, 568) -> [10000 ps] RD @ (1, 576) -> [10000 ps] RD @ (1, 584) -> [10000 ps] RD @ (1, 592) -> -[10000 ps] RD @ (1, 600) -> [10000 ps] RD @ (1, 608) -> [10000 ps] RD @ (1, 616) -> [10000 ps] RD @ (1, 624) -> [10000 ps] RD @ (1, 632) -> -[10000 ps] RD @ (1, 640) -> [10000 ps] RD @ (1, 648) -> [10000 ps] RD @ (1, 656) -> [10000 ps] RD @ (1, 664) -> [10000 ps] RD @ (1, 672) -> -[10000 ps] RD @ (1, 680) -> [10000 ps] RD @ (1, 688) -> [10000 ps] RD @ (1, 696) -> [10000 ps] RD @ (1, 704) -> [10000 ps] RD @ (1, 712) -> -[10000 ps] RD @ (1, 720) -> [10000 ps] RD @ (1, 728) -> [10000 ps] RD @ (1, 736) -> [10000 ps] RD @ (1, 744) -> [10000 ps] RD @ (1, 752) -> -[10000 ps] RD @ (1, 760) -> [10000 ps] RD @ (1, 768) -> [10000 ps] RD @ (1, 776) -> [10000 ps] RD @ (1, 784) -> [10000 ps] RD @ (1, 792) -> -[10000 ps] RD @ (1, 800) -> [10000 ps] RD @ (1, 808) -> [10000 ps] RD @ (1, 816) -> [10000 ps] RD @ (1, 824) -> [10000 ps] RD @ (1, 832) -> -[10000 ps] RD @ (1, 840) -> [10000 ps] RD @ (1, 848) -> [10000 ps] RD @ (1, 856) -> [10000 ps] RD @ (1, 864) -> [10000 ps] RD @ (1, 872) -> -[10000 ps] RD @ (1, 880) -> [10000 ps] RD @ (1, 888) -> [10000 ps] RD @ (1, 896) -> [10000 ps] RD @ (1, 904) -> [10000 ps] RD @ (1, 912) -> -[10000 ps] RD @ (1, 920) -> [10000 ps] RD @ (1, 928) -> [10000 ps] RD @ (1, 936) -> [10000 ps] RD @ (1, 944) -> [10000 ps] RD @ (1, 952) -> -[10000 ps] RD @ (1, 960) -> [10000 ps] RD @ (1, 968) -> [ 5000 ps] ACT @ (2, 16383) -> [ 5000 ps] RD @ (1, 976) -> [10000 ps] RD @ (1, 984) -> -[10000 ps] RD @ (1, 992) -> [10000 ps] RD @ (1, 1000) -> [10000 ps] RD @ (1, 1008) -> [10000 ps] RD @ (1, 1016) -> [10000 ps] RD @ (2, 0) -> -[10000 ps] RD @ (2, 8) -> [10000 ps] RD @ (2, 16) -> [10000 ps] RD @ (2, 24) -> [10000 ps] RD @ (2, 32) -> [10000 ps] RD @ (2, 40) -> -[10000 ps] RD @ (2, 48) -> [10000 ps] RD @ (2, 56) -> [10000 ps] RD @ (2, 64) -> [10000 ps] RD @ (2, 72) -> [10000 ps] RD @ (2, 80) -> -[10000 ps] RD @ (2, 88) -> [10000 ps] RD @ (2, 96) -> [10000 ps] RD @ (2, 104) -> [10000 ps] RD @ (2, 112) -> [10000 ps] RD @ (2, 120) -> -[10000 ps] RD @ (2, 128) -> [10000 ps] RD @ (2, 136) -> [10000 ps] RD @ (2, 144) -> [10000 ps] RD @ (2, 152) -> [10000 ps] RD @ (2, 160) -> -[10000 ps] RD @ (2, 168) -> [10000 ps] RD @ (2, 176) -> [10000 ps] RD @ (2, 184) -> [10000 ps] RD @ (2, 192) -> [10000 ps] RD @ (2, 200) -> -[10000 ps] RD @ (2, 208) -> [10000 ps] RD @ (2, 216) -> [10000 ps] RD @ (2, 224) -> [10000 ps] RD @ (2, 232) -> [10000 ps] RD @ (2, 240) -> -[10000 ps] RD @ (2, 248) -> [10000 ps] RD @ (2, 256) -> [10000 ps] RD @ (2, 264) -> [10000 ps] RD @ (2, 272) -> [10000 ps] RD @ (2, 280) -> -[10000 ps] RD @ (2, 288) -> [10000 ps] RD @ (2, 296) -> [10000 ps] RD @ (2, 304) -> [10000 ps] RD @ (2, 312) -> [10000 ps] RD @ (2, 320) -> -[10000 ps] RD @ (2, 328) -> [10000 ps] RD @ (2, 336) -> [10000 ps] RD @ (2, 344) -> [10000 ps] RD @ (2, 352) -> [10000 ps] RD @ (2, 360) -> -[10000 ps] RD @ (2, 368) -> [10000 ps] RD @ (2, 376) -> [10000 ps] RD @ (2, 384) -> [10000 ps] RD @ (2, 392) -> [10000 ps] RD @ (2, 400) -> -[10000 ps] RD @ (2, 408) -> [10000 ps] RD @ (2, 416) -> [10000 ps] RD @ (2, 424) -> [10000 ps] RD @ (2, 432) -> [10000 ps] RD @ (2, 440) -> -[10000 ps] RD @ (2, 448) -> [10000 ps] RD @ (2, 456) -> [10000 ps] RD @ (2, 464) -> [10000 ps] RD @ (2, 472) -> [10000 ps] RD @ (2, 480) -> -[10000 ps] RD @ (2, 488) -> [10000 ps] RD @ (2, 496) -> [10000 ps] RD @ (2, 504) -> [10000 ps] RD @ (2, 512) -> [10000 ps] RD @ (2, 520) -> -[10000 ps] RD @ (2, 528) -> [10000 ps] RD @ (2, 536) -> [10000 ps] RD @ (2, 544) -> [10000 ps] RD @ (2, 552) -> [10000 ps] RD @ (2, 560) -> -[10000 ps] RD @ (2, 568) -> [10000 ps] RD @ (2, 576) -> [10000 ps] RD @ (2, 584) -> [10000 ps] RD @ (2, 592) -> [10000 ps] RD @ (2, 600) -> -[10000 ps] RD @ (2, 608) -> [10000 ps] RD @ (2, 616) -> [10000 ps] RD @ (2, 624) -> [10000 ps] RD @ (2, 632) -> [10000 ps] RD @ (2, 640) -> -[10000 ps] RD @ (2, 648) -> [10000 ps] RD @ (2, 656) -> [10000 ps] RD @ (2, 664) -> [10000 ps] RD @ (2, 672) -> [10000 ps] RD @ (2, 680) -> -[10000 ps] RD @ (2, 688) -> [10000 ps] RD @ (2, 696) -> [10000 ps] RD @ (2, 704) -> [10000 ps] RD @ (2, 712) -> [10000 ps] RD @ (2, 720) -> -[10000 ps] RD @ (2, 728) -> [10000 ps] RD @ (2, 736) -> [10000 ps] RD @ (2, 744) -> [10000 ps] RD @ (2, 752) -> [10000 ps] RD @ (2, 760) -> -[10000 ps] RD @ (2, 768) -> [10000 ps] RD @ (2, 776) -> [10000 ps] RD @ (2, 784) -> [10000 ps] RD @ (2, 792) -> [10000 ps] RD @ (2, 800) -> -[10000 ps] RD @ (2, 808) -> [10000 ps] RD @ (2, 816) -> [10000 ps] RD @ (2, 824) -> [10000 ps] RD @ (2, 832) -> [10000 ps] RD @ (2, 840) -> -[10000 ps] RD @ (2, 848) -> [10000 ps] RD @ (2, 856) -> [10000 ps] RD @ (2, 864) -> [10000 ps] RD @ (2, 872) -> [10000 ps] RD @ (2, 880) -> -[10000 ps] RD @ (2, 888) -> [10000 ps] RD @ (2, 896) -> [10000 ps] RD @ (2, 904) -> [10000 ps] RD @ (2, 912) -> [10000 ps] RD @ (2, 920) -> -[10000 ps] RD @ (2, 928) -> [10000 ps] RD @ (2, 936) -> [10000 ps] RD @ (2, 944) -> [10000 ps] RD @ (2, 952) -> [10000 ps] RD @ (2, 960) -> -[10000 ps] RD @ (2, 968) -> [ 5000 ps] ACT @ (3, 16383) -> [ 5000 ps] RD @ (2, 976) -> [10000 ps] RD @ (2, 984) -> [10000 ps] RD @ (2, 992) -> -[10000 ps] RD @ (2, 1000) -> [10000 ps] RD @ (2, 1008) -> [10000 ps] RD @ (2, 1016) -> [10000 ps] RD @ (3, 0) -> [10000 ps] RD @ (3, 8) -> -[10000 ps] RD @ (3, 16) -> [10000 ps] RD @ (3, 24) -> [10000 ps] RD @ (3, 32) -> [10000 ps] RD @ (3, 40) -> [10000 ps] RD @ (3, 48) -> -[10000 ps] RD @ (3, 56) -> [10000 ps] RD @ (3, 64) -> [10000 ps] RD @ (3, 72) -> [10000 ps] RD @ (3, 80) -> [10000 ps] RD @ (3, 88) -> -[10000 ps] RD @ (3, 96) -> [10000 ps] RD @ (3, 104) -> [10000 ps] RD @ (3, 112) -> [10000 ps] RD @ (3, 120) -> [10000 ps] RD @ (3, 128) -> -[10000 ps] RD @ (3, 136) -> [10000 ps] RD @ (3, 144) -> [10000 ps] RD @ (3, 152) -> [10000 ps] RD @ (3, 160) -> [10000 ps] RD @ (3, 168) -> -[10000 ps] RD @ (3, 176) -> [10000 ps] RD @ (3, 184) -> [10000 ps] RD @ (3, 192) -> [10000 ps] RD @ (3, 200) -> [10000 ps] RD @ (3, 208) -> -[10000 ps] RD @ (3, 216) -> [10000 ps] RD @ (3, 224) -> [10000 ps] RD @ (3, 232) -> [10000 ps] RD @ (3, 240) -> [10000 ps] RD @ (3, 248) -> -[10000 ps] RD @ (3, 256) -> [10000 ps] RD @ (3, 264) -> [10000 ps] RD @ (3, 272) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (3, 280) -> -[10000 ps] RD @ (3, 288) -> [10000 ps] RD @ (3, 296) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (3, 16383) -> [15000 ps] RD @ (3, 304) -> [10000 ps] RD @ (3, 312) -> [10000 ps] RD @ (3, 320) -> [10000 ps] RD @ (3, 328) -> -[10000 ps] RD @ (3, 336) -> [10000 ps] RD @ (3, 344) -> [10000 ps] RD @ (3, 352) -> [10000 ps] RD @ (3, 360) -> [10000 ps] RD @ (3, 368) -> -[10000 ps] RD @ (3, 376) -> [10000 ps] RD @ (3, 384) -> [10000 ps] RD @ (3, 392) -> [10000 ps] RD @ (3, 400) -> [10000 ps] RD @ (3, 408) -> -[10000 ps] RD @ (3, 416) -> [10000 ps] RD @ (3, 424) -> [10000 ps] RD @ (3, 432) -> [10000 ps] RD @ (3, 440) -> [10000 ps] RD @ (3, 448) -> -[10000 ps] RD @ (3, 456) -> [10000 ps] RD @ (3, 464) -> [10000 ps] RD @ (3, 472) -> [10000 ps] RD @ (3, 480) -> [10000 ps] RD @ (3, 488) -> -[10000 ps] RD @ (3, 496) -> [10000 ps] RD @ (3, 504) -> [10000 ps] RD @ (3, 512) -> [10000 ps] RD @ (3, 520) -> [10000 ps] RD @ (3, 528) -> -[10000 ps] RD @ (3, 536) -> [10000 ps] RD @ (3, 544) -> [10000 ps] RD @ (3, 552) -> [10000 ps] RD @ (3, 560) -> [10000 ps] RD @ (3, 568) -> -[10000 ps] RD @ (3, 576) -> [10000 ps] RD @ (3, 584) -> [10000 ps] RD @ (3, 592) -> [10000 ps] RD @ (3, 600) -> [10000 ps] RD @ (3, 608) -> -[10000 ps] RD @ (3, 616) -> [10000 ps] RD @ (3, 624) -> [10000 ps] RD @ (3, 632) -> [10000 ps] RD @ (3, 640) -> [10000 ps] RD @ (3, 648) -> -[10000 ps] RD @ (3, 656) -> [10000 ps] RD @ (3, 664) -> [10000 ps] RD @ (3, 672) -> [10000 ps] RD @ (3, 680) -> [10000 ps] RD @ (3, 688) -> -[10000 ps] RD @ (3, 696) -> [10000 ps] RD @ (3, 704) -> [10000 ps] RD @ (3, 712) -> [10000 ps] RD @ (3, 720) -> [10000 ps] RD @ (3, 728) -> -[10000 ps] RD @ (3, 736) -> [10000 ps] RD @ (3, 744) -> [10000 ps] RD @ (3, 752) -> [10000 ps] RD @ (3, 760) -> [10000 ps] RD @ (3, 768) -> -[10000 ps] RD @ (3, 776) -> [10000 ps] RD @ (3, 784) -> [10000 ps] RD @ (3, 792) -> [10000 ps] RD @ (3, 800) -> [10000 ps] RD @ (3, 808) -> -[10000 ps] RD @ (3, 816) -> [10000 ps] RD @ (3, 824) -> [10000 ps] RD @ (3, 832) -> [10000 ps] RD @ (3, 840) -> [10000 ps] RD @ (3, 848) -> -[10000 ps] RD @ (3, 856) -> [10000 ps] RD @ (3, 864) -> [10000 ps] RD @ (3, 872) -> [10000 ps] RD @ (3, 880) -> [10000 ps] RD @ (3, 888) -> -[10000 ps] RD @ (3, 896) -> [10000 ps] RD @ (3, 904) -> [10000 ps] RD @ (3, 912) -> [10000 ps] RD @ (3, 920) -> [10000 ps] RD @ (3, 928) -> -[10000 ps] RD @ (3, 936) -> [10000 ps] RD @ (3, 944) -> [10000 ps] RD @ (3, 952) -> [10000 ps] RD @ (3, 960) -> [10000 ps] RD @ (3, 968) -> -[ 5000 ps] ACT @ (4, 16383) -> [ 5000 ps] RD @ (3, 976) -> [10000 ps] RD @ (3, 984) -> [10000 ps] RD @ (3, 992) -> [10000 ps] RD @ (3, 1000) -> -[10000 ps] RD @ (3, 1008) -> [10000 ps] RD @ (3, 1016) -> [10000 ps] RD @ (4, 0) -> [10000 ps] RD @ (4, 8) -> [10000 ps] RD @ (4, 16) -> -[10000 ps] RD @ (4, 24) -> [10000 ps] RD @ (4, 32) -> [10000 ps] RD @ (4, 40) -> [10000 ps] RD @ (4, 48) -> [10000 ps] RD @ (4, 56) -> -[10000 ps] RD @ (4, 64) -> [10000 ps] RD @ (4, 72) -> [10000 ps] RD @ (4, 80) -> [10000 ps] RD @ (4, 88) -> [10000 ps] RD @ (4, 96) -> -[10000 ps] RD @ (4, 104) -> [10000 ps] RD @ (4, 112) -> [10000 ps] RD @ (4, 120) -> [10000 ps] RD @ (4, 128) -> [10000 ps] RD @ (4, 136) -> -[10000 ps] RD @ (4, 144) -> [10000 ps] RD @ (4, 152) -> [10000 ps] RD @ (4, 160) -> [10000 ps] RD @ (4, 168) -> [10000 ps] RD @ (4, 176) -> -[10000 ps] RD @ (4, 184) -> [10000 ps] RD @ (4, 192) -> [10000 ps] RD @ (4, 200) -> [10000 ps] RD @ (4, 208) -> [10000 ps] RD @ (4, 216) -> -[10000 ps] RD @ (4, 224) -> [10000 ps] RD @ (4, 232) -> [10000 ps] RD @ (4, 240) -> [10000 ps] RD @ (4, 248) -> [10000 ps] RD @ (4, 256) -> -[10000 ps] RD @ (4, 264) -> [10000 ps] RD @ (4, 272) -> [10000 ps] RD @ (4, 280) -> [10000 ps] RD @ (4, 288) -> [10000 ps] RD @ (4, 296) -> -[10000 ps] RD @ (4, 304) -> [10000 ps] RD @ (4, 312) -> [10000 ps] RD @ (4, 320) -> [10000 ps] RD @ (4, 328) -> [10000 ps] RD @ (4, 336) -> -[10000 ps] RD @ (4, 344) -> [10000 ps] RD @ (4, 352) -> [10000 ps] RD @ (4, 360) -> [10000 ps] RD @ (4, 368) -> [10000 ps] RD @ (4, 376) -> -[10000 ps] RD @ (4, 384) -> [10000 ps] RD @ (4, 392) -> [10000 ps] RD @ (4, 400) -> [10000 ps] RD @ (4, 408) -> [10000 ps] RD @ (4, 416) -> -[10000 ps] RD @ (4, 424) -> [10000 ps] RD @ (4, 432) -> [10000 ps] RD @ (4, 440) -> [10000 ps] RD @ (4, 448) -> [10000 ps] RD @ (4, 456) -> -[10000 ps] RD @ (4, 464) -> [10000 ps] RD @ (4, 472) -> [10000 ps] RD @ (4, 480) -> [10000 ps] RD @ (4, 488) -> [10000 ps] RD @ (4, 496) -> -[10000 ps] RD @ (4, 504) -> [10000 ps] RD @ (4, 512) -> [10000 ps] RD @ (4, 520) -> [10000 ps] RD @ (4, 528) -> [10000 ps] RD @ (4, 536) -> -[10000 ps] RD @ (4, 544) -> [10000 ps] RD @ (4, 552) -> [10000 ps] RD @ (4, 560) -> [10000 ps] RD @ (4, 568) -> [10000 ps] RD @ (4, 576) -> -[10000 ps] RD @ (4, 584) -> [10000 ps] RD @ (4, 592) -> [10000 ps] RD @ (4, 600) -> [10000 ps] RD @ (4, 608) -> [10000 ps] RD @ (4, 616) -> -[10000 ps] RD @ (4, 624) -> [10000 ps] RD @ (4, 632) -> [10000 ps] RD @ (4, 640) -> [10000 ps] RD @ (4, 648) -> [10000 ps] RD @ (4, 656) -> -[10000 ps] RD @ (4, 664) -> [10000 ps] RD @ (4, 672) -> [10000 ps] RD @ (4, 680) -> [10000 ps] RD @ (4, 688) -> [10000 ps] RD @ (4, 696) -> -[10000 ps] RD @ (4, 704) -> [10000 ps] RD @ (4, 712) -> [10000 ps] RD @ (4, 720) -> [10000 ps] RD @ (4, 728) -> [10000 ps] RD @ (4, 736) -> -[10000 ps] RD @ (4, 744) -> [10000 ps] RD @ (4, 752) -> [10000 ps] RD @ (4, 760) -> [10000 ps] RD @ (4, 768) -> [10000 ps] RD @ (4, 776) -> -[10000 ps] RD @ (4, 784) -> [10000 ps] RD @ (4, 792) -> [10000 ps] RD @ (4, 800) -> [10000 ps] RD @ (4, 808) -> [10000 ps] RD @ (4, 816) -> -[10000 ps] RD @ (4, 824) -> [10000 ps] RD @ (4, 832) -> [10000 ps] RD @ (4, 840) -> [10000 ps] RD @ (4, 848) -> [10000 ps] RD @ (4, 856) -> -[10000 ps] RD @ (4, 864) -> [10000 ps] RD @ (4, 872) -> [10000 ps] RD @ (4, 880) -> [10000 ps] RD @ (4, 888) -> [10000 ps] RD @ (4, 896) -> -[10000 ps] RD @ (4, 904) -> [10000 ps] RD @ (4, 912) -> [10000 ps] RD @ (4, 920) -> [10000 ps] RD @ (4, 928) -> [10000 ps] RD @ (4, 936) -> -[10000 ps] RD @ (4, 944) -> [10000 ps] RD @ (4, 952) -> [10000 ps] RD @ (4, 960) -> [10000 ps] RD @ (4, 968) -> [ 5000 ps] ACT @ (5, 16383) -> -[ 5000 ps] RD @ (4, 976) -> [10000 ps] RD @ (4, 984) -> [10000 ps] RD @ (4, 992) -> [10000 ps] RD @ (4, 1000) -> [10000 ps] RD @ (4, 1008) -> -[10000 ps] RD @ (4, 1016) -> [10000 ps] RD @ (5, 0) -> [10000 ps] RD @ (5, 8) -> [10000 ps] RD @ (5, 16) -> [10000 ps] RD @ (5, 24) -> -[10000 ps] RD @ (5, 32) -> [10000 ps] RD @ (5, 40) -> [10000 ps] RD @ (5, 48) -> [10000 ps] RD @ (5, 56) -> [10000 ps] RD @ (5, 64) -> -[10000 ps] RD @ (5, 72) -> [10000 ps] RD @ (5, 80) -> [10000 ps] RD @ (5, 88) -> [10000 ps] RD @ (5, 96) -> [10000 ps] RD @ (5, 104) -> -[10000 ps] RD @ (5, 112) -> [10000 ps] RD @ (5, 120) -> [10000 ps] RD @ (5, 128) -> [10000 ps] RD @ (5, 136) -> [10000 ps] RD @ (5, 144) -> -[10000 ps] RD @ (5, 152) -> [10000 ps] RD @ (5, 160) -> [10000 ps] RD @ (5, 168) -> [10000 ps] RD @ (5, 176) -> [10000 ps] RD @ (5, 184) -> -[10000 ps] RD @ (5, 192) -> [10000 ps] RD @ (5, 200) -> [10000 ps] RD @ (5, 208) -> [10000 ps] RD @ (5, 216) -> [10000 ps] RD @ (5, 224) -> -[10000 ps] RD @ (5, 232) -> [10000 ps] RD @ (5, 240) -> [10000 ps] RD @ (5, 248) -> [10000 ps] RD @ (5, 256) -> [10000 ps] RD @ (5, 264) -> -[10000 ps] RD @ (5, 272) -> [10000 ps] RD @ (5, 280) -> [10000 ps] RD @ (5, 288) -> [10000 ps] RD @ (5, 296) -> [10000 ps] RD @ (5, 304) -> -[10000 ps] RD @ (5, 312) -> [10000 ps] RD @ (5, 320) -> [10000 ps] RD @ (5, 328) -> [10000 ps] RD @ (5, 336) -> [10000 ps] RD @ (5, 344) -> -[10000 ps] RD @ (5, 352) -> [10000 ps] RD @ (5, 360) -> [10000 ps] RD @ (5, 368) -> [10000 ps] RD @ (5, 376) -> [10000 ps] RD @ (5, 384) -> -[10000 ps] RD @ (5, 392) -> [10000 ps] RD @ (5, 400) -> [10000 ps] RD @ (5, 408) -> [10000 ps] RD @ (5, 416) -> [10000 ps] RD @ (5, 424) -> -[10000 ps] RD @ (5, 432) -> [10000 ps] RD @ (5, 440) -> [10000 ps] RD @ (5, 448) -> [10000 ps] RD @ (5, 456) -> [10000 ps] RD @ (5, 464) -> -[10000 ps] RD @ (5, 472) -> [10000 ps] RD @ (5, 480) -> [10000 ps] RD @ (5, 488) -> [10000 ps] RD @ (5, 496) -> [10000 ps] RD @ (5, 504) -> -[10000 ps] RD @ (5, 512) -> [10000 ps] RD @ (5, 520) -> [10000 ps] RD @ (5, 528) -> [10000 ps] RD @ (5, 536) -> [10000 ps] RD @ (5, 544) -> -[10000 ps] RD @ (5, 552) -> [10000 ps] RD @ (5, 560) -> [10000 ps] RD @ (5, 568) -> [10000 ps] RD @ (5, 576) -> [10000 ps] RD @ (5, 584) -> -[10000 ps] RD @ (5, 592) -> [10000 ps] RD @ (5, 600) -> [10000 ps] RD @ (5, 608) -> [10000 ps] RD @ (5, 616) -> [10000 ps] RD @ (5, 624) -> -[10000 ps] RD @ (5, 632) -> [10000 ps] RD @ (5, 640) -> [10000 ps] RD @ (5, 648) -> [10000 ps] RD @ (5, 656) -> [10000 ps] RD @ (5, 664) -> -[10000 ps] RD @ (5, 672) -> [10000 ps] RD @ (5, 680) -> [10000 ps] RD @ (5, 688) -> [10000 ps] RD @ (5, 696) -> [10000 ps] RD @ (5, 704) -> -[10000 ps] RD @ (5, 712) -> [10000 ps] RD @ (5, 720) -> [10000 ps] RD @ (5, 728) -> [10000 ps] RD @ (5, 736) -> [10000 ps] RD @ (5, 744) -> -[10000 ps] RD @ (5, 752) -> [10000 ps] RD @ (5, 760) -> [10000 ps] RD @ (5, 768) -> [10000 ps] RD @ (5, 776) -> [10000 ps] RD @ (5, 784) -> -[10000 ps] RD @ (5, 792) -> [10000 ps] RD @ (5, 800) -> [10000 ps] RD @ (5, 808) -> [10000 ps] RD @ (5, 816) -> [10000 ps] RD @ (5, 824) -> -[10000 ps] RD @ (5, 832) -> [10000 ps] RD @ (5, 840) -> [10000 ps] RD @ (5, 848) -> [10000 ps] RD @ (5, 856) -> [10000 ps] RD @ (5, 864) -> -[10000 ps] RD @ (5, 872) -> [10000 ps] RD @ (5, 880) -> [10000 ps] RD @ (5, 888) -> [10000 ps] RD @ (5, 896) -> [10000 ps] RD @ (5, 904) -> -[10000 ps] RD @ (5, 912) -> [10000 ps] RD @ (5, 920) -> [10000 ps] RD @ (5, 928) -> [10000 ps] RD @ (5, 936) -> [10000 ps] RD @ (5, 944) -> -[10000 ps] RD @ (5, 952) -> [10000 ps] RD @ (5, 960) -> [10000 ps] RD @ (5, 968) -> [ 5000 ps] ACT @ (6, 16383) -> [ 5000 ps] RD @ (5, 976) -> -[10000 ps] RD @ (5, 984) -> [10000 ps] RD @ (5, 992) -> [10000 ps] RD @ (5, 1000) -> [10000 ps] RD @ (5, 1008) -> [10000 ps] RD @ (5, 1016) -> -[10000 ps] RD @ (6, 0) -> [10000 ps] RD @ (6, 8) -> [10000 ps] RD @ (6, 16) -> [10000 ps] RD @ (6, 24) -> [10000 ps] RD @ (6, 32) -> -[10000 ps] RD @ (6, 40) -> [10000 ps] RD @ (6, 48) -> [10000 ps] RD @ (6, 56) -> [10000 ps] RD @ (6, 64) -> [10000 ps] RD @ (6, 72) -> -[10000 ps] RD @ (6, 80) -> [10000 ps] RD @ (6, 88) -> [10000 ps] RD @ (6, 96) -> [10000 ps] RD @ (6, 104) -> [10000 ps] RD @ (6, 112) -> -[10000 ps] RD @ (6, 120) -> [10000 ps] RD @ (6, 128) -> [10000 ps] RD @ (6, 136) -> [10000 ps] RD @ (6, 144) -> [10000 ps] RD @ (6, 152) -> -[10000 ps] RD @ (6, 160) -> [10000 ps] RD @ (6, 168) -> [10000 ps] RD @ (6, 176) -> [10000 ps] RD @ (6, 184) -> [10000 ps] RD @ (6, 192) -> -[10000 ps] RD @ (6, 200) -> [10000 ps] RD @ (6, 208) -> [10000 ps] RD @ (6, 216) -> [10000 ps] RD @ (6, 224) -> [10000 ps] RD @ (6, 232) -> -[10000 ps] RD @ (6, 240) -> [10000 ps] RD @ (6, 248) -> [10000 ps] RD @ (6, 256) -> [10000 ps] RD @ (6, 264) -> [10000 ps] RD @ (6, 272) -> -[10000 ps] RD @ (6, 280) -> [10000 ps] RD @ (6, 288) -> [10000 ps] RD @ (6, 296) -> [10000 ps] RD @ (6, 304) -> [10000 ps] RD @ (6, 312) -> -[10000 ps] RD @ (6, 320) -> [10000 ps] RD @ (6, 328) -> [10000 ps] RD @ (6, 336) -> [10000 ps] RD @ (6, 344) -> [10000 ps] RD @ (6, 352) -> -[10000 ps] RD @ (6, 360) -> [10000 ps] RD @ (6, 368) -> [10000 ps] RD @ (6, 376) -> [10000 ps] RD @ (6, 384) -> [10000 ps] RD @ (6, 392) -> -[10000 ps] RD @ (6, 400) -> [10000 ps] RD @ (6, 408) -> [10000 ps] RD @ (6, 416) -> [10000 ps] RD @ (6, 424) -> [10000 ps] RD @ (6, 432) -> -[10000 ps] RD @ (6, 440) -> [10000 ps] RD @ (6, 448) -> [10000 ps] RD @ (6, 456) -> [10000 ps] RD @ (6, 464) -> [10000 ps] RD @ (6, 472) -> -[10000 ps] RD @ (6, 480) -> [10000 ps] RD @ (6, 488) -> [10000 ps] RD @ (6, 496) -> [10000 ps] RD @ (6, 504) -> [10000 ps] RD @ (6, 512) -> -[10000 ps] RD @ (6, 520) -> [10000 ps] RD @ (6, 528) -> [10000 ps] RD @ (6, 536) -> [10000 ps] RD @ (6, 544) -> [10000 ps] RD @ (6, 552) -> -[10000 ps] RD @ (6, 560) -> [10000 ps] RD @ (6, 568) -> [10000 ps] RD @ (6, 576) -> [10000 ps] RD @ (6, 584) -> [10000 ps] RD @ (6, 592) -> -[10000 ps] RD @ (6, 600) -> [10000 ps] RD @ (6, 608) -> [10000 ps] RD @ (6, 616) -> [10000 ps] RD @ (6, 624) -> [10000 ps] RD @ (6, 632) -> -[10000 ps] RD @ (6, 640) -> [10000 ps] RD @ (6, 648) -> [10000 ps] RD @ (6, 656) -> [10000 ps] RD @ (6, 664) -> [10000 ps] RD @ (6, 672) -> -[10000 ps] RD @ (6, 680) -> [10000 ps] RD @ (6, 688) -> [10000 ps] RD @ (6, 696) -> [10000 ps] RD @ (6, 704) -> [10000 ps] RD @ (6, 712) -> -[10000 ps] RD @ (6, 720) -> [10000 ps] RD @ (6, 728) -> [10000 ps] RD @ (6, 736) -> [10000 ps] RD @ (6, 744) -> [10000 ps] RD @ (6, 752) -> -[10000 ps] RD @ (6, 760) -> [10000 ps] RD @ (6, 768) -> [10000 ps] RD @ (6, 776) -> [10000 ps] RD @ (6, 784) -> [10000 ps] RD @ (6, 792) -> -[10000 ps] RD @ (6, 800) -> [10000 ps] RD @ (6, 808) -> [10000 ps] RD @ (6, 816) -> [10000 ps] RD @ (6, 824) -> [10000 ps] RD @ (6, 832) -> -[10000 ps] RD @ (6, 840) -> [10000 ps] RD @ (6, 848) -> [10000 ps] RD @ (6, 856) -> [10000 ps] RD @ (6, 864) -> [10000 ps] RD @ (6, 872) -> -[10000 ps] RD @ (6, 880) -> [10000 ps] RD @ (6, 888) -> [10000 ps] RD @ (6, 896) -> [10000 ps] RD @ (6, 904) -> [10000 ps] RD @ (6, 912) -> -[10000 ps] RD @ (6, 920) -> [10000 ps] RD @ (6, 928) -> [10000 ps] RD @ (6, 936) -> [10000 ps] RD @ (6, 944) -> [10000 ps] RD @ (6, 952) -> -[10000 ps] RD @ (6, 960) -> [10000 ps] RD @ (6, 968) -> [ 5000 ps] ACT @ (7, 16383) -> [ 5000 ps] RD @ (6, 976) -> [10000 ps] RD @ (6, 984) -> -[10000 ps] RD @ (6, 992) -> [10000 ps] RD @ (6, 1000) -> [10000 ps] RD @ (6, 1008) -> [10000 ps] RD @ (6, 1016) -> [10000 ps] RD @ (7, 0) -> -[10000 ps] RD @ (7, 8) -> [10000 ps] RD @ (7, 16) -> [10000 ps] RD @ (7, 24) -> [10000 ps] RD @ (7, 32) -> [10000 ps] RD @ (7, 40) -> -[10000 ps] RD @ (7, 48) -> [10000 ps] RD @ (7, 56) -> [10000 ps] RD @ (7, 64) -> [10000 ps] RD @ (7, 72) -> [10000 ps] RD @ (7, 80) -> -[10000 ps] RD @ (7, 88) -> [10000 ps] RD @ (7, 96) -> [10000 ps] RD @ (7, 104) -> [10000 ps] RD @ (7, 112) -> [10000 ps] RD @ (7, 120) -> -[10000 ps] RD @ (7, 128) -> [10000 ps] RD @ (7, 136) -> [10000 ps] RD @ (7, 144) -> [10000 ps] RD @ (7, 152) -> [10000 ps] RD @ (7, 160) -> -[10000 ps] RD @ (7, 168) -> [10000 ps] RD @ (7, 176) -> [10000 ps] RD @ (7, 184) -> [10000 ps] RD @ (7, 192) -> [10000 ps] RD @ (7, 200) -> -[10000 ps] RD @ (7, 208) -> [10000 ps] RD @ (7, 216) -> [10000 ps] RD @ (7, 224) -> [10000 ps] RD @ (7, 232) -> [10000 ps] RD @ (7, 240) -> -[10000 ps] RD @ (7, 248) -> [10000 ps] RD @ (7, 256) -> [10000 ps] RD @ (7, 264) -> [10000 ps] RD @ (7, 272) -> [10000 ps] RD @ (7, 280) -> -[10000 ps] RD @ (7, 288) -> [10000 ps] RD @ (7, 296) -> [10000 ps] RD @ (7, 304) -> [10000 ps] RD @ (7, 312) -> [10000 ps] RD @ (7, 320) -> -[10000 ps] RD @ (7, 328) -> [10000 ps] RD @ (7, 336) -> [10000 ps] RD @ (7, 344) -> [10000 ps] RD @ (7, 352) -> [10000 ps] RD @ (7, 360) -> -[10000 ps] RD @ (7, 368) -> [10000 ps] RD @ (7, 376) -> [10000 ps] RD @ (7, 384) -> [10000 ps] RD @ (7, 392) -> [10000 ps] RD @ (7, 400) -> -[10000 ps] RD @ (7, 408) -> [10000 ps] RD @ (7, 416) -> [10000 ps] RD @ (7, 424) -> [10000 ps] RD @ (7, 432) -> [10000 ps] RD @ (7, 440) -> -[10000 ps] RD @ (7, 448) -> [10000 ps] RD @ (7, 456) -> [10000 ps] RD @ (7, 464) -> [10000 ps] RD @ (7, 472) -> [10000 ps] RD @ (7, 480) -> -[10000 ps] RD @ (7, 488) -> [10000 ps] RD @ (7, 496) -> [10000 ps] RD @ (7, 504) -> [10000 ps] RD @ (7, 512) -> [10000 ps] RD @ (7, 520) -> -[10000 ps] RD @ (7, 528) -> [10000 ps] RD @ (7, 536) -> [10000 ps] RD @ (7, 544) -> [10000 ps] RD @ (7, 552) -> [10000 ps] RD @ (7, 560) -> -[10000 ps] RD @ (7, 568) -> [10000 ps] RD @ (7, 576) -> [10000 ps] RD @ (7, 584) -> [10000 ps] RD @ (7, 592) -> [10000 ps] RD @ (7, 600) -> -[10000 ps] RD @ (7, 608) -> [10000 ps] RD @ (7, 616) -> [10000 ps] RD @ (7, 624) -> [10000 ps] RD @ (7, 632) -> [10000 ps] RD @ (7, 640) -> -[10000 ps] RD @ (7, 648) -> [10000 ps] RD @ (7, 656) -> [10000 ps] RD @ (7, 664) -> [10000 ps] RD @ (7, 672) -> [10000 ps] RD @ (7, 680) -> -[10000 ps] RD @ (7, 688) -> [10000 ps] RD @ (7, 696) -> [10000 ps] RD @ (7, 704) -> [10000 ps] RD @ (7, 712) -> [10000 ps] RD @ (7, 720) -> -[10000 ps] RD @ (7, 728) -> [10000 ps] RD @ (7, 736) -> [10000 ps] RD @ (7, 744) -> [10000 ps] RD @ (7, 752) -> [10000 ps] RD @ (7, 760) -> -[10000 ps] RD @ (7, 768) -> [10000 ps] RD @ (7, 776) -> [10000 ps] RD @ (7, 784) -> [10000 ps] RD @ (7, 792) -> [10000 ps] RD @ (7, 800) -> -[10000 ps] RD @ (7, 808) -> [10000 ps] RD @ (7, 816) -> [10000 ps] RD @ (7, 824) -> [10000 ps] RD @ (7, 832) -> [10000 ps] RD @ (7, 840) -> -[10000 ps] RD @ (7, 848) -> [10000 ps] RD @ (7, 856) -> [10000 ps] RD @ (7, 864) -> [10000 ps] RD @ (7, 872) -> [10000 ps] RD @ (7, 880) -> -[10000 ps] RD @ (7, 888) -> [10000 ps] RD @ (7, 896) -> [10000 ps] RD @ (7, 904) -> [10000 ps] RD @ (7, 912) -> [10000 ps] RD @ (7, 920) -> -[10000 ps] RD @ (7, 928) -> [10000 ps] RD @ (7, 936) -> [10000 ps] RD @ (7, 944) -> [10000 ps] RD @ (7, 952) -> [10000 ps] RD @ (7, 960) -> -[10000 ps] RD @ (7, 968) -> [ 5000 ps] ACT @ (0, 0) -> [ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (7, 984) -> [10000 ps] RD @ (7, 992) -> -[10000 ps] RD @ (7, 1000) -> [10000 ps] RD @ (7, 1008) -> [10000 ps] RD @ (7, 1016) -> [10000 ps] RD @ (0, 0) -> [10000 ps] RD @ (0, 8) -> -[10000 ps] RD @ (0, 16) -> [10000 ps] RD @ (0, 24) -> [10000 ps] RD @ (0, 32) -> [10000 ps] RD @ (0, 40) -> [10000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (0, 56) -> [10000 ps] RD @ (0, 64) -> [10000 ps] RD @ (0, 72) -> [10000 ps] RD @ (0, 80) -> [10000 ps] RD @ (0, 88) -> -[10000 ps] RD @ (0, 96) -> [10000 ps] RD @ (0, 104) -> [10000 ps] RD @ (0, 112) -> [10000 ps] RD @ (0, 120) -> [10000 ps] RD @ (0, 128) -> -[10000 ps] RD @ (0, 136) -> [10000 ps] RD @ (0, 144) -> [10000 ps] RD @ (0, 152) -> [10000 ps] RD @ (0, 160) -> [10000 ps] RD @ (0, 168) -> -[10000 ps] RD @ (0, 176) -> [10000 ps] RD @ (0, 184) -> [10000 ps] RD @ (0, 192) -> [10000 ps] RD @ (0, 200) -> [10000 ps] RD @ (0, 208) -> -[10000 ps] RD @ (0, 216) -> [10000 ps] RD @ (0, 224) -> [10000 ps] RD @ (0, 232) -> [10000 ps] RD @ (0, 240) -> [10000 ps] RD @ (0, 248) -> -[10000 ps] RD @ (0, 256) -> [10000 ps] RD @ (0, 264) -> [10000 ps] RD @ (0, 272) -> [10000 ps] RD @ (0, 280) -> [10000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (0, 296) -> [10000 ps] RD @ (0, 304) -> [10000 ps] RD @ (0, 312) -> [10000 ps] RD @ (0, 320) -> [10000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (0, 336) -> [10000 ps] RD @ (0, 344) -> [10000 ps] RD @ (0, 352) -> [10000 ps] RD @ (0, 360) -> [10000 ps] RD @ (0, 368) -> -[10000 ps] RD @ (0, 376) -> [10000 ps] RD @ (0, 384) -> [10000 ps] RD @ (0, 392) -> [10000 ps] RD @ (0, 400) -> [10000 ps] RD @ (0, 408) -> -[10000 ps] RD @ (0, 416) -> [10000 ps] RD @ (0, 424) -> [10000 ps] RD @ (0, 432) -> [10000 ps] RD @ (0, 440) -> [10000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (0, 456) -> [10000 ps] RD @ (0, 464) -> [10000 ps] RD @ (0, 472) -> [10000 ps] RD @ (0, 480) -> [10000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (0, 496) -> [10000 ps] RD @ (0, 504) -> [10000 ps] RD @ (0, 512) -> [10000 ps] RD @ (0, 520) -> [10000 ps] RD @ (0, 528) -> -[10000 ps] RD @ (0, 536) -> [10000 ps] RD @ (0, 544) -> [10000 ps] RD @ (0, 552) -> [10000 ps] RD @ (0, 560) -> [10000 ps] RD @ (0, 568) -> -[10000 ps] RD @ (0, 576) -> [10000 ps] RD @ (0, 584) -> [10000 ps] RD @ (0, 592) -> [10000 ps] RD @ (0, 600) -> [10000 ps] RD @ (0, 608) -> -[10000 ps] RD @ (0, 616) -> [10000 ps] RD @ (0, 624) -> [10000 ps] RD @ (0, 632) -> [10000 ps] RD @ (0, 640) -> [10000 ps] RD @ (0, 648) -> -[10000 ps] RD @ (0, 656) -> [10000 ps] RD @ (0, 664) -> [10000 ps] RD @ (0, 672) -> [10000 ps] RD @ (0, 680) -> [10000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (0, 696) -> [10000 ps] RD @ (0, 704) -> [10000 ps] RD @ (0, 712) -> [10000 ps] RD @ (0, 720) -> [10000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (0, 736) -> [10000 ps] RD @ (0, 744) -> [10000 ps] RD @ (0, 752) -> [10000 ps] RD @ (0, 760) -> [10000 ps] RD @ (0, 768) -> -[10000 ps] RD @ (0, 776) -> [10000 ps] RD @ (0, 784) -> [10000 ps] RD @ (0, 792) -> [10000 ps] RD @ (0, 800) -> [10000 ps] RD @ (0, 808) -> -[10000 ps] RD @ (0, 816) -> [10000 ps] RD @ (0, 824) -> [10000 ps] RD @ (0, 832) -> [10000 ps] RD @ (0, 840) -> [10000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (0, 856) -> [10000 ps] RD @ (0, 864) -> [10000 ps] RD @ (0, 872) -> [10000 ps] RD @ (0, 880) -> [10000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (0, 896) -> [10000 ps] RD @ (0, 904) -> [10000 ps] RD @ (0, 912) -> [10000 ps] RD @ (0, 920) -> [10000 ps] RD @ (0, 928) -> -[10000 ps] RD @ (0, 936) -> [10000 ps] RD @ (0, 944) -> [10000 ps] RD @ (0, 952) -> [10000 ps] RD @ (0, 960) -> [10000 ps] RD @ (0, 968) -> -[ 5000 ps] ACT @ (1, 0) -> [ 5000 ps] RD @ (0, 976) -> [10000 ps] RD @ (0, 984) -> --------------------------------- -DONE TEST 1: LAST ROW -Number of Operations: 2304 -Time Started: 99430 ns -Time Done: 124000 ns -Average Rate: 10 ns/request --------------------------------- - - -[10000 ps] RD @ (0, 992) -> [10000 ps] RD @ (0, 1000) -> -[10000 ps] RD @ (0, 1008) -> [10000 ps] RD @ (0, 1016) -> FAILED: Address = 16777342, expected data = 585c7fb0585b71b0585a63b0585955b0585849b058573bb058562db058551fb0585411b0585303b05851f5b05850e7b0584fd9b0584ecbb0584dbfb0584cb1b0, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 124080000.0 ps -[97500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2852) -> -[10000 ps] ACT @ (0, 1773) -> [ 7500 ps] WR @ (4, 960) -> [10000 ps] WR @ (0, 960) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [17500 ps] WR @ (0, 960) -> [10000 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14919) -> [17500 ps] WR @ (4, 952) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [22500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13840) -> [17500 ps] WR @ (4, 952) -> [10000 ps] WR @ (0, 952) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 10602) -> [10000 ps] ACT @ (0, 11682) -> [17500 ps] WR @ (0, 952) -> [ 5000 ps] NOP -> [ 5000 ps] WR @ (4, 952) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9523) -> [17500 ps] WR @ (4, 952) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8444) -> -[17500 ps] WR @ (4, 952) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 7365) -> -[17500 ps] WR @ (0, 944) -> [ 2500 ps] ACT @ (4, 5206) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6286) -> [17500 ps] WR @ (0, 944) -> -[10000 ps] WR @ (4, 944) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4127) -> [17500 ps] WR @ (4, 944) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1969) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3048) -> [17500 ps] WR @ (4, 944) -> [10000 ps] WR @ (0, 944) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16194) -> [10000 ps] ACT @ (0, 890) -> [17500 ps] WR @ (0, 944) -> -[10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15115) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12957) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14036) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 936) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10798) -> [10000 ps] ACT @ (0, 11878) -> [17500 ps] WR @ (0, 936) -> -[10000 ps] WR @ (4, 936) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9719) -> [17500 ps] WR @ (4, 936) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7561) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8640) -> [17500 ps] WR @ (4, 936) -> [10000 ps] WR @ (0, 928) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5402) -> [10000 ps] ACT @ (0, 6482) -> [17500 ps] WR @ (0, 928) -> -[10000 ps] WR @ (4, 928) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4323) -> [17500 ps] WR @ (4, 928) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2165) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3244) -> [17500 ps] WR @ (4, 928) -> [10000 ps] WR @ (0, 928) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6) -> [10000 ps] ACT @ (0, 1086) -> [17500 ps] WR @ (0, 928) -> -[10000 ps] WR @ (4, 928) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> -[17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [17500 ps] WR @ (0, 920) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [17500 ps] WR @ (0, 920) -> -[10000 ps] WR @ (4, 920) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8836) -> [10000 ps] ACT @ (4, 9915) -> -[17500 ps] WR @ (4, 920) -> [10000 ps] WR @ (0, 920) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [17500 ps] WR @ (0, 912) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [17500 ps] WR @ (0, 912) -> -[10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3440) -> [10000 ps] ACT @ (4, 4519) -> -[17500 ps] WR @ (4, 912) -> [10000 ps] WR @ (0, 912) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [17500 ps] WR @ (0, 912) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [17500 ps] WR @ (0, 912) -> -[10000 ps] WR @ (4, 912) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14428) -> [10000 ps] ACT @ (4, 15507) -> -[17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [17500 ps] WR @ (0, 904) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [17500 ps] WR @ (0, 904) -> -[10000 ps] WR @ (4, 904) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9032) -> [10000 ps] ACT @ (4, 10111) -> -[17500 ps] WR @ (4, 904) -> [10000 ps] WR @ (0, 904) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [17500 ps] WR @ (0, 896) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [17500 ps] WR @ (0, 896) -> -[10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3636) -> [10000 ps] ACT @ (4, 4715) -> -[17500 ps] WR @ (4, 896) -> [10000 ps] WR @ (0, 896) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [17500 ps] WR @ (0, 896) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [17500 ps] WR @ (0, 896) -> -[10000 ps] WR @ (4, 896) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14624) -> [10000 ps] ACT @ (4, 15703) -> -[17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> -[10000 ps] ACT @ (0, 13545) -> [17500 ps] WR @ (0, 888) -> [10000 ps] WR @ (4, 888) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> -[17500 ps] WR @ (4, 888) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9228) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> -[17500 ps] WR @ (4, 888) -> [10000 ps] WR @ (0, 888) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7069) -> -[10000 ps] ACT @ (0, 8149) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> -[17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3832) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> -[17500 ps] WR @ (4, 880) -> [10000 ps] WR @ (0, 880) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1673) -> -[10000 ps] ACT @ (0, 2753) -> [17500 ps] WR @ (0, 880) -> [10000 ps] WR @ (4, 880) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> -[17500 ps] WR @ (4, 880) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14820) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> -[17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12661) -> -[10000 ps] ACT @ (0, 13741) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 872) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> -[17500 ps] WR @ (4, 872) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9424) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> -[17500 ps] WR @ (4, 872) -> [10000 ps] WR @ (0, 872) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7265) -> -[10000 ps] ACT @ (0, 8345) -> [17500 ps] WR @ (0, 872) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> -[17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4028) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> -[17500 ps] WR @ (4, 864) -> [10000 ps] WR @ (0, 864) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1869) -> -[10000 ps] ACT @ (0, 2949) -> [17500 ps] WR @ (0, 864) -> [10000 ps] WR @ (4, 864) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> -[17500 ps] WR @ (4, 864) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15016) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> -[17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12857) -> -[10000 ps] ACT @ (0, 13937) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 856) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> [17500 ps] WR @ (4, 856) -> [10000 ps] WR @ (0, 856) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9620) -> [17500 ps] WR @ (0, 856) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8541) -> [17500 ps] WR @ (0, 856) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5303) -> [10000 ps] ACT @ (4, 6382) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 848) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4224) -> [17500 ps] WR @ (0, 848) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3145) -> [17500 ps] WR @ (0, 848) -> [10000 ps] WR @ (4, 848) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 16291) -> [10000 ps] ACT @ (4, 986) -> [17500 ps] WR @ (4, 848) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15212) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14133) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 840) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10895) -> [10000 ps] ACT @ (4, 11974) -> [17500 ps] WR @ (4, 840) -> [10000 ps] WR @ (0, 840) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9816) -> [17500 ps] WR @ (0, 840) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8737) -> [17500 ps] WR @ (0, 840) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5499) -> [10000 ps] ACT @ (4, 6578) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4420) -> [17500 ps] WR @ (0, 832) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3341) -> [17500 ps] WR @ (0, 832) -> [10000 ps] WR @ (4, 832) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 103) -> [10000 ps] ACT @ (4, 1182) -> [17500 ps] WR @ (4, 832) -> [10000 ps] WR @ (0, 832) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15408) -> [17500 ps] WR @ (0, 824) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14329) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11091) -> [10000 ps] ACT @ (4, 12170) -> [17500 ps] WR @ (4, 824) -> [10000 ps] WR @ (0, 824) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [17500 ps] WR @ (0, 824) -> [10000 ps] WR @ (4, 824) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7853) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6774) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3536) -> [10000 ps] ACT @ (0, 4616) -> [17500 ps] WR @ (0, 816) -> [10000 ps] WR @ (4, 816) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2457) -> [17500 ps] WR @ (4, 816) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1378) -> [17500 ps] WR @ (4, 816) -> [10000 ps] WR @ (0, 816) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14524) -> [10000 ps] ACT @ (0, 15604) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13445) -> [17500 ps] WR @ (4, 808) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12366) -> [17500 ps] WR @ (4, 808) -> [10000 ps] WR @ (0, 808) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9128) -> [10000 ps] ACT @ (0, 10208) -> [17500 ps] WR @ (0, 808) -> [10000 ps] WR @ (4, 808) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8049) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6970) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3732) -> [10000 ps] ACT @ (0, 4812) -> [17500 ps] WR @ (0, 800) -> [10000 ps] WR @ (4, 800) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2653) -> [17500 ps] WR @ (4, 800) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1574) -> [17500 ps] WR @ (4, 800) -> [10000 ps] WR @ (0, 800) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14720) -> [10000 ps] ACT @ (0, 15800) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13641) -> [17500 ps] WR @ (4, 792) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12562) -> [17500 ps] WR @ (4, 792) -> [10000 ps] WR @ (0, 792) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9324) -> [10000 ps] ACT @ (0, 10404) -> [17500 ps] WR @ (0, 792) -> [10000 ps] WR @ (4, 792) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [17500 ps] WR @ (4, 792) -> -[10000 ps] WR @ (0, 784) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 6087) -> -[17500 ps] WR @ (0, 784) -> [ 2500 ps] ACT @ (4, 3928) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [17500 ps] WR @ (0, 784) -> -[10000 ps] WR @ (4, 784) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1770) -> [10000 ps] ACT @ (4, 2849) -> -[17500 ps] WR @ (4, 784) -> [10000 ps] WR @ (0, 784) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [17500 ps] WR @ (0, 784) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [17500 ps] WR @ (0, 776) -> -[10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12758) -> [10000 ps] ACT @ (4, 13837) -> -[17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 776) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [17500 ps] WR @ (0, 776) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [17500 ps] WR @ (0, 776) -> -[10000 ps] WR @ (4, 776) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7362) -> [10000 ps] ACT @ (4, 8441) -> -[17500 ps] WR @ (4, 776) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [17500 ps] WR @ (0, 768) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [17500 ps] WR @ (0, 768) -> -[10000 ps] WR @ (4, 768) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1966) -> [10000 ps] ACT @ (4, 3045) -> -[17500 ps] WR @ (4, 768) -> [10000 ps] WR @ (0, 768) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [17500 ps] WR @ (0, 768) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [17500 ps] WR @ (0, 760) -> -[10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12954) -> [10000 ps] ACT @ (4, 14033) -> -[17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 760) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [17500 ps] WR @ (0, 760) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [17500 ps] WR @ (0, 760) -> -[10000 ps] WR @ (4, 760) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7558) -> [10000 ps] ACT @ (4, 8637) -> -[17500 ps] WR @ (4, 760) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> -[10000 ps] ACT @ (0, 6479) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> -[17500 ps] WR @ (4, 752) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2162) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> -[17500 ps] WR @ (4, 752) -> [10000 ps] WR @ (0, 752) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3) -> -[10000 ps] ACT @ (0, 1083) -> [17500 ps] WR @ (0, 752) -> [10000 ps] WR @ (4, 752) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> -[17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13150) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> -[17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 744) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10991) -> -[10000 ps] ACT @ (0, 12071) -> [17500 ps] WR @ (0, 744) -> [10000 ps] WR @ (4, 744) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> -[17500 ps] WR @ (4, 744) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7754) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> -[17500 ps] WR @ (4, 744) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5595) -> -[10000 ps] ACT @ (0, 6675) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> -[17500 ps] WR @ (4, 736) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2358) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> -[17500 ps] WR @ (4, 736) -> [10000 ps] WR @ (0, 736) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 199) -> -[10000 ps] ACT @ (0, 1279) -> [17500 ps] WR @ (0, 736) -> [10000 ps] WR @ (4, 736) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> -[17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13346) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> -[17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 728) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11187) -> -[10000 ps] ACT @ (0, 12267) -> [17500 ps] WR @ (0, 728) -> [10000 ps] WR @ (4, 728) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> -[17500 ps] WR @ (4, 728) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7950) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> -[17500 ps] WR @ (4, 728) -> [10000 ps] WR @ (0, 720) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5791) -> -[10000 ps] ACT @ (0, 6871) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> [17500 ps] WR @ (4, 720) -> [10000 ps] WR @ (0, 720) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2554) -> [17500 ps] WR @ (0, 720) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1475) -> [17500 ps] WR @ (0, 720) -> [10000 ps] WR @ (4, 720) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14621) -> [10000 ps] ACT @ (4, 15700) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13542) -> [17500 ps] WR @ (0, 712) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12463) -> [17500 ps] WR @ (0, 712) -> [10000 ps] WR @ (4, 712) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9225) -> [10000 ps] ACT @ (4, 10304) -> [17500 ps] WR @ (4, 712) -> [10000 ps] WR @ (0, 712) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8146) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7067) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 3829) -> [10000 ps] ACT @ (4, 4908) -> [17500 ps] WR @ (4, 704) -> [10000 ps] WR @ (0, 704) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2750) -> [17500 ps] WR @ (0, 704) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1671) -> [17500 ps] WR @ (0, 704) -> [10000 ps] WR @ (4, 704) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 14817) -> [10000 ps] ACT @ (4, 15896) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13738) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12659) -> [17500 ps] WR @ (0, 696) -> [10000 ps] WR @ (4, 696) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 9421) -> [10000 ps] ACT @ (4, 10500) -> [17500 ps] WR @ (4, 696) -> [10000 ps] WR @ (0, 696) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8342) -> [17500 ps] WR @ (0, 696) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7263) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4025) -> [10000 ps] ACT @ (4, 5104) -> [17500 ps] WR @ (4, 688) -> [10000 ps] WR @ (0, 688) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> [10000 ps] ACT @ (0, 2946) -> [17500 ps] WR @ (0, 688) -> [10000 ps] WR @ (4, 688) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> [17500 ps] WR @ (4, 688) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12854) -> [10000 ps] ACT @ (0, 13934) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 680) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> [17500 ps] WR @ (4, 680) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> [17500 ps] WR @ (4, 680) -> [10000 ps] WR @ (0, 680) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7458) -> [10000 ps] ACT @ (0, 8538) -> [17500 ps] WR @ (0, 680) -> [10000 ps] WR @ (4, 672) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> [17500 ps] WR @ (4, 672) -> [10000 ps] WR @ (0, 672) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2062) -> [10000 ps] ACT @ (0, 3142) -> [17500 ps] WR @ (0, 672) -> [10000 ps] WR @ (4, 672) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> [17500 ps] WR @ (4, 672) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13050) -> [10000 ps] ACT @ (0, 14130) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 664) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> [17500 ps] WR @ (4, 664) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> [17500 ps] WR @ (4, 664) -> [10000 ps] WR @ (0, 664) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7654) -> [10000 ps] ACT @ (0, 8734) -> [17500 ps] WR @ (0, 664) -> [10000 ps] WR @ (4, 656) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> [17500 ps] WR @ (4, 656) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> [17500 ps] WR @ (4, 656) -> [10000 ps] WR @ (0, 656) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2258) -> [10000 ps] ACT @ (0, 3338) -> [17500 ps] WR @ (0, 656) -> [10000 ps] WR @ (4, 656) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [17500 ps] WR @ (4, 656) -> -[10000 ps] WR @ (0, 656) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15405) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13246) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14326) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 648) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11088) -> [10000 ps] ACT @ (4, 12167) -> [17500 ps] WR @ (4, 648) -> -[10000 ps] WR @ (0, 648) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10009) -> [17500 ps] WR @ (0, 648) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7850) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8930) -> [17500 ps] WR @ (0, 648) -> [10000 ps] WR @ (4, 640) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5692) -> [10000 ps] ACT @ (4, 6771) -> [17500 ps] WR @ (4, 640) -> -[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4613) -> [17500 ps] WR @ (0, 640) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2454) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3534) -> [17500 ps] WR @ (0, 640) -> [10000 ps] WR @ (4, 640) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 296) -> [10000 ps] ACT @ (4, 1375) -> [17500 ps] WR @ (4, 640) -> -[10000 ps] WR @ (0, 640) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15601) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13442) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14522) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 632) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11284) -> [10000 ps] ACT @ (4, 12363) -> [17500 ps] WR @ (4, 632) -> -[10000 ps] WR @ (0, 632) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10205) -> [17500 ps] WR @ (0, 632) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8046) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9126) -> [17500 ps] WR @ (0, 632) -> [10000 ps] WR @ (4, 624) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5888) -> [10000 ps] ACT @ (4, 6967) -> [17500 ps] WR @ (4, 624) -> -[10000 ps] WR @ (0, 624) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 4809) -> -[17500 ps] WR @ (0, 624) -> [ 2500 ps] ACT @ (4, 2650) -> [42500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> [17500 ps] WR @ (0, 624) -> -[10000 ps] WR @ (4, 624) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 492) -> [10000 ps] ACT @ (4, 1571) -> -[17500 ps] WR @ (4, 624) -> [10000 ps] WR @ (0, 624) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14717) -> -[10000 ps] ACT @ (0, 15797) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> -[17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> -[17500 ps] WR @ (4, 616) -> [10000 ps] WR @ (0, 616) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9321) -> -[10000 ps] ACT @ (0, 10401) -> [17500 ps] WR @ (0, 616) -> [10000 ps] WR @ (4, 616) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> -[17500 ps] WR @ (4, 616) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> -[17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3925) -> -[10000 ps] ACT @ (0, 5005) -> [17500 ps] WR @ (0, 608) -> [10000 ps] WR @ (4, 608) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> -[17500 ps] WR @ (4, 608) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> -[17500 ps] WR @ (4, 608) -> [10000 ps] WR @ (0, 608) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14913) -> -[10000 ps] ACT @ (0, 15993) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> -[17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> -[17500 ps] WR @ (4, 600) -> [10000 ps] WR @ (0, 600) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9517) -> -[10000 ps] ACT @ (0, 10597) -> [17500 ps] WR @ (0, 600) -> [10000 ps] WR @ (4, 600) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> -[17500 ps] WR @ (4, 600) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> -[17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4121) -> -[10000 ps] ACT @ (0, 5201) -> [17500 ps] WR @ (0, 592) -> [10000 ps] WR @ (4, 592) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> -[17500 ps] WR @ (4, 592) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> -[17500 ps] WR @ (4, 592) -> [10000 ps] WR @ (0, 592) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15109) -> -[10000 ps] ACT @ (0, 16189) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12951) -> [10000 ps] ACT @ (4, 14030) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 584) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11872) -> [17500 ps] WR @ (0, 584) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10793) -> [17500 ps] WR @ (0, 584) -> [10000 ps] WR @ (4, 584) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7555) -> [10000 ps] ACT @ (4, 8634) -> [17500 ps] WR @ (4, 584) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6476) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5397) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 576) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2159) -> [10000 ps] ACT @ (4, 3238) -> [17500 ps] WR @ (4, 576) -> [10000 ps] WR @ (0, 576) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1080) -> [17500 ps] WR @ (0, 576) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1) -> [17500 ps] WR @ (0, 576) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13147) -> [10000 ps] ACT @ (4, 14226) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 568) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12068) -> [17500 ps] WR @ (0, 568) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10989) -> [17500 ps] WR @ (0, 568) -> [10000 ps] WR @ (4, 568) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7751) -> [10000 ps] ACT @ (4, 8830) -> [17500 ps] WR @ (4, 568) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6672) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5593) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 560) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2355) -> [10000 ps] ACT @ (4, 3434) -> [17500 ps] WR @ (4, 560) -> [10000 ps] WR @ (0, 560) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1276) -> [17500 ps] WR @ (0, 560) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 197) -> [17500 ps] WR @ (0, 560) -> [10000 ps] WR @ (4, 552) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13343) -> [10000 ps] ACT @ (4, 14422) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 552) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [17500 ps] WR @ (0, 552) -> [10000 ps] WR @ (4, 552) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10105) -> [17500 ps] WR @ (4, 552) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9026) -> [17500 ps] WR @ (4, 552) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5788) -> [10000 ps] ACT @ (0, 6868) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4709) -> [17500 ps] WR @ (4, 544) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3630) -> [17500 ps] WR @ (4, 544) -> [10000 ps] WR @ (0, 544) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 392) -> [10000 ps] ACT @ (0, 1472) -> [17500 ps] WR @ (0, 544) -> [10000 ps] WR @ (4, 544) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15697) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14618) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 536) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11380) -> [10000 ps] ACT @ (0, 12460) -> [17500 ps] WR @ (0, 536) -> [10000 ps] WR @ (4, 536) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10301) -> [17500 ps] WR @ (4, 536) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9222) -> [17500 ps] WR @ (4, 536) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5984) -> [10000 ps] ACT @ (0, 7064) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4905) -> [17500 ps] WR @ (4, 528) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3826) -> [17500 ps] WR @ (4, 528) -> [10000 ps] WR @ (0, 528) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 588) -> [10000 ps] ACT @ (0, 1668) -> [17500 ps] WR @ (0, 528) -> [10000 ps] WR @ (4, 528) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15893) -> [17500 ps] WR @ (4, 520) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14814) -> [17500 ps] WR @ (4, 520) -> [10000 ps] WR @ (0, 520) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11576) -> [10000 ps] ACT @ (0, 12656) -> [17500 ps] WR @ (0, 520) -> [10000 ps] WR @ (4, 520) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [17500 ps] WR @ (4, 520) -> -[10000 ps] WR @ (0, 520) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [17500 ps] WR @ (0, 520) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6180) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4022) -> [10000 ps] ACT @ (4, 5101) -> [17500 ps] WR @ (4, 512) -> -[10000 ps] WR @ (0, 512) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [17500 ps] WR @ (0, 512) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 784) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [17500 ps] WR @ (0, 512) -> [10000 ps] WR @ (4, 512) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15010) -> [10000 ps] ACT @ (4, 16089) -> [17500 ps] WR @ (4, 504) -> -[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11772) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [17500 ps] WR @ (0, 504) -> [10000 ps] WR @ (4, 504) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9614) -> [10000 ps] ACT @ (4, 10693) -> [17500 ps] WR @ (4, 504) -> -[10000 ps] WR @ (0, 504) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [17500 ps] WR @ (0, 504) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6376) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4218) -> [10000 ps] ACT @ (4, 5297) -> [17500 ps] WR @ (4, 496) -> -[10000 ps] WR @ (0, 496) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [17500 ps] WR @ (0, 496) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 980) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [17500 ps] WR @ (0, 496) -> [10000 ps] WR @ (4, 496) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15206) -> [10000 ps] ACT @ (4, 16285) -> [17500 ps] WR @ (4, 488) -> -[10000 ps] WR @ (0, 488) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [17500 ps] WR @ (0, 488) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11968) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 488) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9810) -> [10000 ps] ACT @ (4, 10889) -> [17500 ps] WR @ (4, 488) -> -[10000 ps] WR @ (0, 488) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> -[17500 ps] WR @ (0, 488) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [17500 ps] WR @ (4, 480) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4414) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [17500 ps] WR @ (4, 480) -> -[10000 ps] WR @ (0, 480) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2255) -> [10000 ps] ACT @ (0, 3335) -> -[17500 ps] WR @ (0, 480) -> [10000 ps] WR @ (4, 480) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [17500 ps] WR @ (4, 480) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15402) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [17500 ps] WR @ (4, 480) -> -[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13243) -> [10000 ps] ACT @ (0, 14323) -> -[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 472) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [17500 ps] WR @ (4, 472) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10006) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [17500 ps] WR @ (4, 472) -> -[10000 ps] WR @ (0, 472) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7847) -> [10000 ps] ACT @ (0, 8927) -> -[17500 ps] WR @ (0, 472) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [17500 ps] WR @ (4, 464) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4610) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [17500 ps] WR @ (4, 464) -> -[10000 ps] WR @ (0, 464) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (0, 3531) -> -[10000 ps] ACT @ (4, 2451) -> [ 7500 ps] WR @ (0, 464) -> [10000 ps] WR @ (4, 464) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> -[17500 ps] WR @ (4, 464) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15598) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> -[17500 ps] WR @ (4, 464) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13439) -> -[10000 ps] ACT @ (0, 14519) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 456) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> -[17500 ps] WR @ (4, 456) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10202) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> -[17500 ps] WR @ (4, 456) -> [10000 ps] WR @ (0, 456) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8043) -> -[10000 ps] ACT @ (0, 9123) -> [17500 ps] WR @ (0, 456) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4806) -> [17500 ps] WR @ (0, 448) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3727) -> [17500 ps] WR @ (0, 448) -> [10000 ps] WR @ (4, 448) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 489) -> [10000 ps] ACT @ (4, 1568) -> [17500 ps] WR @ (4, 448) -> [10000 ps] WR @ (0, 448) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15794) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14715) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11477) -> [10000 ps] ACT @ (4, 12556) -> [17500 ps] WR @ (4, 440) -> [10000 ps] WR @ (0, 440) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10398) -> [17500 ps] WR @ (0, 440) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9319) -> [17500 ps] WR @ (0, 440) -> [10000 ps] WR @ (4, 440) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6081) -> [10000 ps] ACT @ (4, 7160) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5002) -> [17500 ps] WR @ (0, 432) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3923) -> [17500 ps] WR @ (0, 432) -> [10000 ps] WR @ (4, 432) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 685) -> [10000 ps] ACT @ (4, 1764) -> [17500 ps] WR @ (4, 432) -> [10000 ps] WR @ (0, 432) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15990) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14911) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11673) -> [10000 ps] ACT @ (4, 12752) -> [17500 ps] WR @ (4, 424) -> [10000 ps] WR @ (0, 424) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10594) -> [17500 ps] WR @ (0, 424) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9515) -> [17500 ps] WR @ (0, 424) -> [10000 ps] WR @ (4, 424) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6277) -> [10000 ps] ACT @ (4, 7356) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> [10000 ps] ACT @ (0, 5198) -> [17500 ps] WR @ (0, 416) -> [10000 ps] WR @ (4, 416) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> [17500 ps] WR @ (4, 416) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> [17500 ps] WR @ (4, 416) -> [10000 ps] WR @ (0, 416) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15106) -> [10000 ps] ACT @ (0, 16186) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> [17500 ps] WR @ (4, 408) -> [10000 ps] WR @ (0, 408) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9710) -> [10000 ps] ACT @ (0, 10790) -> [17500 ps] WR @ (0, 408) -> [10000 ps] WR @ (4, 408) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> [17500 ps] WR @ (4, 408) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4314) -> [10000 ps] ACT @ (0, 5394) -> [17500 ps] WR @ (0, 400) -> [10000 ps] WR @ (4, 400) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3235) -> [17500 ps] WR @ (4, 400) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2156) -> [17500 ps] WR @ (4, 400) -> [10000 ps] WR @ (0, 400) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15302) -> [10000 ps] ACT @ (0, 16382) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14223) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13144) -> [17500 ps] WR @ (4, 392) -> [10000 ps] WR @ (0, 392) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9906) -> [10000 ps] ACT @ (0, 10986) -> [17500 ps] WR @ (0, 392) -> [10000 ps] WR @ (4, 392) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8827) -> [17500 ps] WR @ (4, 392) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7748) -> [17500 ps] WR @ (4, 384) -> [10000 ps] WR @ (0, 384) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4510) -> [10000 ps] ACT @ (0, 5590) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 384) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [17500 ps] WR @ (4, 384) -> -[10000 ps] WR @ (0, 384) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [17500 ps] WR @ (0, 384) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15498) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [17500 ps] WR @ (0, 384) -> [10000 ps] WR @ (4, 376) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13340) -> [10000 ps] ACT @ (4, 14419) -> [17500 ps] WR @ (4, 376) -> -[10000 ps] WR @ (0, 376) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [17500 ps] WR @ (0, 376) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10102) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [17500 ps] WR @ (0, 376) -> [10000 ps] WR @ (4, 376) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7944) -> [10000 ps] ACT @ (4, 9023) -> [17500 ps] WR @ (4, 376) -> -[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4706) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 368) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2548) -> [10000 ps] ACT @ (4, 3627) -> [17500 ps] WR @ (4, 368) -> -[10000 ps] WR @ (0, 368) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [17500 ps] WR @ (0, 368) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15694) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [17500 ps] WR @ (0, 368) -> [10000 ps] WR @ (4, 360) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13536) -> [10000 ps] ACT @ (4, 14615) -> [17500 ps] WR @ (4, 360) -> -[10000 ps] WR @ (0, 360) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [17500 ps] WR @ (0, 360) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10298) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [17500 ps] WR @ (0, 360) -> [10000 ps] WR @ (4, 360) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8140) -> [10000 ps] ACT @ (4, 9219) -> [17500 ps] WR @ (4, 360) -> -[10000 ps] WR @ (0, 352) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [17500 ps] WR @ (0, 352) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4902) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> -[35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2744) -> [10000 ps] ACT @ (4, 3823) -> [17500 ps] WR @ (4, 352) -> -[10000 ps] WR @ (0, 352) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> -[17500 ps] WR @ (0, 352) -> [10000 ps] WR @ (4, 352) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [17500 ps] WR @ (4, 344) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13732) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [17500 ps] WR @ (4, 344) -> -[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11573) -> [10000 ps] ACT @ (0, 12653) -> -[17500 ps] WR @ (0, 344) -> [10000 ps] WR @ (4, 344) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [17500 ps] WR @ (4, 344) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8336) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [17500 ps] WR @ (4, 344) -> -[10000 ps] WR @ (0, 344) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6177) -> [10000 ps] ACT @ (0, 7257) -> -[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [17500 ps] WR @ (4, 336) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2940) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [17500 ps] WR @ (4, 336) -> -[10000 ps] WR @ (0, 336) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 781) -> [10000 ps] ACT @ (0, 1861) -> -[17500 ps] WR @ (0, 336) -> [10000 ps] WR @ (4, 336) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [17500 ps] WR @ (4, 328) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13928) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [17500 ps] WR @ (4, 328) -> -[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11769) -> [10000 ps] ACT @ (0, 12849) -> -[17500 ps] WR @ (0, 328) -> [10000 ps] WR @ (4, 328) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [17500 ps] WR @ (4, 328) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8532) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [17500 ps] WR @ (4, 328) -> -[10000 ps] WR @ (0, 328) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6373) -> [10000 ps] ACT @ (0, 7453) -> -[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [17500 ps] WR @ (4, 320) -> -[ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3136) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [17500 ps] WR @ (4, 320) -> -[10000 ps] WR @ (0, 320) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 977) -> [10000 ps] ACT @ (0, 2057) -> -[17500 ps] WR @ (0, 320) -> [10000 ps] WR @ (4, 320) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> -[10000 ps] ACT @ (4, 16282) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> -[17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> -[17500 ps] WR @ (0, 312) -> [10000 ps] WR @ (4, 312) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9807) -> -[10000 ps] ACT @ (4, 10886) -> [17500 ps] WR @ (4, 312) -> [10000 ps] WR @ (0, 312) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> -[17500 ps] WR @ (0, 312) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> -[17500 ps] WR @ (0, 304) -> [10000 ps] WR @ (4, 304) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4411) -> -[10000 ps] ACT @ (4, 5490) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 304) -> [35000 ps] NOP -> [10000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3332) -> [17500 ps] WR @ (0, 304) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [17500 ps] WR @ (0, 304) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 1173) -> [17500 ps] WR @ (4, 304) -> -[ 2500 ps] ACT @ (0, 15399) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 94) -> [17500 ps] WR @ (4, 304) -> [10000 ps] WR @ (0, 296) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [17500 ps] WR @ (0, 296) -> [10000 ps] WR @ (4, 296) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10003) -> [10000 ps] ACT @ (4, 11082) -> [17500 ps] WR @ (4, 296) -> [10000 ps] WR @ (0, 296) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [17500 ps] WR @ (0, 296) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4607) -> [10000 ps] ACT @ (4, 5686) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 288) -> -[45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [17500 ps] WR @ (0, 288) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> -[22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [17500 ps] WR @ (0, 288) -> [10000 ps] WR @ (4, 288) -> [35000 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15595) -> [10000 ps] ACT @ (4, 290) -> [17500 ps] WR @ (4, 288) -> [10000 ps] WR @ (0, 280) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> [10000 ps] ACT @ (0, 14516) -> [17500 ps] WR @ (0, 280) -> -[10000 ps] WR @ (4, 280) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> [17500 ps] WR @ (4, 280) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10199) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> [17500 ps] WR @ (4, 280) -> [10000 ps] WR @ (0, 280) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8040) -> [10000 ps] ACT @ (0, 9120) -> [17500 ps] WR @ (0, 280) -> -[10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4803) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 272) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2644) -> [10000 ps] ACT @ (0, 3724) -> [17500 ps] WR @ (0, 272) -> -[10000 ps] WR @ (4, 272) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> [17500 ps] WR @ (4, 272) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15791) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> [17500 ps] WR @ (4, 272) -> [10000 ps] WR @ (0, 264) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13632) -> [10000 ps] ACT @ (0, 14712) -> [17500 ps] WR @ (0, 264) -> -[10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> [17500 ps] WR @ (4, 264) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10395) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> [17500 ps] WR @ (4, 264) -> [10000 ps] WR @ (0, 264) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8236) -> [10000 ps] ACT @ (0, 9316) -> [17500 ps] WR @ (0, 264) -> -[10000 ps] WR @ (4, 264) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4999) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 256) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2840) -> [10000 ps] ACT @ (0, 3920) -> [17500 ps] WR @ (0, 256) -> -[10000 ps] WR @ (4, 256) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> [17500 ps] WR @ (4, 256) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15987) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> [17500 ps] WR @ (4, 256) -> [10000 ps] WR @ (0, 248) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13828) -> [10000 ps] ACT @ (0, 14908) -> [17500 ps] WR @ (0, 248) -> -[10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> -[17500 ps] WR @ (4, 248) -> [10000 ps] WR @ (0, 248) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10591) -> [17500 ps] WR @ (0, 248) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9512) -> [17500 ps] WR @ (0, 248) -> -[10000 ps] WR @ (4, 248) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6274) -> [10000 ps] ACT @ (4, 7353) -> -[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5195) -> [17500 ps] WR @ (0, 240) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4116) -> [17500 ps] WR @ (0, 240) -> -[10000 ps] WR @ (4, 240) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 878) -> [10000 ps] ACT @ (4, 1957) -> -[17500 ps] WR @ (4, 240) -> [10000 ps] WR @ (0, 240) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16183) -> [17500 ps] WR @ (0, 232) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15104) -> [17500 ps] WR @ (0, 232) -> -[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11866) -> [10000 ps] ACT @ (4, 12945) -> -[17500 ps] WR @ (4, 232) -> [10000 ps] WR @ (0, 232) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10787) -> [17500 ps] WR @ (0, 232) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9708) -> [17500 ps] WR @ (0, 232) -> -[10000 ps] WR @ (4, 232) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6470) -> [10000 ps] ACT @ (4, 7549) -> -[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5391) -> [17500 ps] WR @ (0, 224) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4312) -> [17500 ps] WR @ (0, 224) -> -[10000 ps] WR @ (4, 224) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1074) -> [10000 ps] ACT @ (4, 2153) -> -[17500 ps] WR @ (4, 224) -> [10000 ps] WR @ (0, 224) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16379) -> [17500 ps] WR @ (0, 216) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15300) -> [17500 ps] WR @ (0, 216) -> -[10000 ps] WR @ (4, 216) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12062) -> [10000 ps] ACT @ (4, 13141) -> -[17500 ps] WR @ (4, 216) -> [10000 ps] WR @ (0, 216) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> -[10000 ps] ACT @ (0, 10983) -> [17500 ps] WR @ (0, 216) -> [10000 ps] WR @ (4, 216) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> -[17500 ps] WR @ (4, 216) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> -[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4507) -> -[10000 ps] ACT @ (0, 5587) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 208) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> -[17500 ps] WR @ (4, 208) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> -[17500 ps] WR @ (4, 208) -> [10000 ps] WR @ (0, 208) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15495) -> -[10000 ps] ACT @ (0, 191) -> [17500 ps] WR @ (0, 208) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> -[17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> -[17500 ps] WR @ (4, 200) -> [10000 ps] WR @ (0, 200) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10099) -> -[10000 ps] ACT @ (0, 11179) -> [17500 ps] WR @ (0, 200) -> [10000 ps] WR @ (4, 200) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> -[17500 ps] WR @ (4, 200) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> -[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4703) -> -[10000 ps] ACT @ (0, 5783) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 192) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> -[17500 ps] WR @ (4, 192) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> -[17500 ps] WR @ (4, 192) -> [10000 ps] WR @ (0, 192) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15691) -> -[10000 ps] ACT @ (0, 387) -> [17500 ps] WR @ (0, 192) -> [10000 ps] WR @ (4, 184) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> -[17500 ps] WR @ (4, 184) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> -[17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 184) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10295) -> -[10000 ps] ACT @ (0, 11375) -> [17500 ps] WR @ (0, 184) -> [10000 ps] WR @ (4, 184) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> [17500 ps] WR @ (4, 184) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7058) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5979) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 176) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2741) -> [10000 ps] ACT @ (4, 3820) -> [17500 ps] WR @ (4, 176) -> [10000 ps] WR @ (0, 176) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1662) -> [17500 ps] WR @ (0, 176) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 583) -> [17500 ps] WR @ (0, 176) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13729) -> [10000 ps] ACT @ (4, 14808) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12650) -> [17500 ps] WR @ (0, 168) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11571) -> [17500 ps] WR @ (0, 168) -> [10000 ps] WR @ (4, 168) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8333) -> [10000 ps] ACT @ (4, 9412) -> [17500 ps] WR @ (4, 168) -> [10000 ps] WR @ (0, 168) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7254) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 6175) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 160) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2937) -> [10000 ps] ACT @ (4, 4016) -> [17500 ps] WR @ (4, 160) -> [10000 ps] WR @ (0, 160) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 1858) -> [17500 ps] WR @ (0, 160) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 779) -> [17500 ps] WR @ (0, 160) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13925) -> [10000 ps] ACT @ (4, 15004) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 12846) -> [17500 ps] WR @ (0, 152) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11767) -> [17500 ps] WR @ (0, 152) -> [10000 ps] WR @ (4, 152) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 8529) -> [10000 ps] ACT @ (4, 9608) -> [17500 ps] WR @ (4, 152) -> [10000 ps] WR @ (0, 152) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5291) -> [17500 ps] WR @ (4, 144) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4212) -> [17500 ps] WR @ (4, 144) -> [10000 ps] WR @ (0, 144) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 974) -> [10000 ps] ACT @ (0, 2054) -> [17500 ps] WR @ (0, 144) -> [10000 ps] WR @ (4, 144) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 16279) -> [17500 ps] WR @ (4, 136) -> -[ 2500 ps] ACT @ (0, 14121) -> [42500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15200) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11962) -> [10000 ps] ACT @ (0, 13042) -> [17500 ps] WR @ (0, 136) -> -[10000 ps] WR @ (4, 136) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10883) -> [17500 ps] WR @ (4, 136) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8725) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9804) -> [17500 ps] WR @ (4, 136) -> [10000 ps] WR @ (0, 136) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6566) -> [10000 ps] ACT @ (0, 7646) -> [17500 ps] WR @ (0, 128) -> -[10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5487) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3329) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4408) -> [17500 ps] WR @ (4, 128) -> [10000 ps] WR @ (0, 128) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1170) -> [10000 ps] ACT @ (0, 2250) -> [17500 ps] WR @ (0, 128) -> -[10000 ps] WR @ (4, 128) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 91) -> [17500 ps] WR @ (4, 128) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14317) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15396) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12158) -> [10000 ps] ACT @ (0, 13238) -> [17500 ps] WR @ (0, 120) -> -[10000 ps] WR @ (4, 120) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11079) -> [17500 ps] WR @ (4, 120) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8921) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10000) -> [17500 ps] WR @ (4, 120) -> [10000 ps] WR @ (0, 120) -> -[35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6762) -> [10000 ps] ACT @ (0, 7842) -> [17500 ps] WR @ (0, 112) -> -[10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> -[17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 112) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [17500 ps] WR @ (0, 112) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [17500 ps] WR @ (0, 112) -> -[10000 ps] WR @ (4, 112) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15592) -> [10000 ps] ACT @ (4, 287) -> -[17500 ps] WR @ (4, 112) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [17500 ps] WR @ (0, 104) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [17500 ps] WR @ (0, 104) -> -[10000 ps] WR @ (4, 104) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10196) -> [10000 ps] ACT @ (4, 11275) -> -[17500 ps] WR @ (4, 104) -> [10000 ps] WR @ (0, 104) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [17500 ps] WR @ (0, 104) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [17500 ps] WR @ (0, 96) -> -[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4800) -> [10000 ps] ACT @ (4, 5879) -> -[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 96) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [17500 ps] WR @ (0, 96) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [17500 ps] WR @ (0, 96) -> -[10000 ps] WR @ (4, 96) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15788) -> [10000 ps] ACT @ (4, 483) -> -[17500 ps] WR @ (4, 96) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [17500 ps] WR @ (0, 88) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [17500 ps] WR @ (0, 88) -> -[10000 ps] WR @ (4, 88) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10392) -> [10000 ps] ACT @ (4, 11471) -> -[17500 ps] WR @ (4, 88) -> [10000 ps] WR @ (0, 88) -> [45000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [17500 ps] WR @ (0, 88) -> -[ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [17500 ps] WR @ (0, 88) -> -[10000 ps] WR @ (4, 80) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4996) -> [10000 ps] ACT @ (4, 6075) -> -[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 80) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> -[10000 ps] ACT @ (0, 3917) -> [17500 ps] WR @ (0, 80) -> [10000 ps] WR @ (4, 80) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> -[17500 ps] WR @ (4, 80) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15984) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> -[17500 ps] WR @ (4, 80) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13825) -> -[10000 ps] ACT @ (0, 14905) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> -[17500 ps] WR @ (4, 72) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10588) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> -[17500 ps] WR @ (4, 72) -> [10000 ps] WR @ (0, 72) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8429) -> -[10000 ps] ACT @ (0, 9509) -> [17500 ps] WR @ (0, 72) -> [10000 ps] WR @ (4, 72) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> -[17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5192) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> -[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 64) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3033) -> -[10000 ps] ACT @ (0, 4113) -> [17500 ps] WR @ (0, 64) -> [10000 ps] WR @ (4, 64) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> -[17500 ps] WR @ (4, 64) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16180) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> -[17500 ps] WR @ (4, 64) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14021) -> -[10000 ps] ACT @ (0, 15101) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> -[17500 ps] WR @ (4, 56) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10784) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> -[17500 ps] WR @ (4, 56) -> [10000 ps] WR @ (0, 56) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8625) -> -[10000 ps] ACT @ (0, 9705) -> [17500 ps] WR @ (0, 56) -> [10000 ps] WR @ (4, 56) -> [45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> -[17500 ps] WR @ (4, 48) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5388) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> -[17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [35000 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3229) -> -[10000 ps] ACT @ (0, 4309) -> [17500 ps] WR @ (0, 48) -> [10000 ps] WR @ (4, 48) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> [17500 ps] WR @ (4, 48) -> [10000 ps] WR @ (0, 48) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16376) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15297) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12059) -> [10000 ps] ACT @ (4, 13138) -> [17500 ps] WR @ (4, 40) -> [10000 ps] WR @ (0, 40) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10980) -> [17500 ps] WR @ (0, 40) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9901) -> [17500 ps] WR @ (0, 40) -> [10000 ps] WR @ (4, 40) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6663) -> [10000 ps] ACT @ (4, 7742) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5584) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4505) -> [17500 ps] WR @ (0, 32) -> [10000 ps] WR @ (4, 32) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1267) -> [10000 ps] ACT @ (4, 2346) -> [17500 ps] WR @ (4, 32) -> [10000 ps] WR @ (0, 32) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 188) -> [17500 ps] WR @ (0, 32) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15493) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12255) -> [10000 ps] ACT @ (4, 13334) -> [17500 ps] WR @ (4, 24) -> [10000 ps] WR @ (0, 24) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 11176) -> [17500 ps] WR @ (0, 24) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10097) -> [17500 ps] WR @ (0, 24) -> [10000 ps] WR @ (4, 24) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6859) -> [10000 ps] ACT @ (4, 7938) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5780) -> [17500 ps] WR @ (0, 16) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [22500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4701) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 16) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1463) -> [10000 ps] ACT @ (4, 2542) -> [17500 ps] WR @ (4, 16) -> [10000 ps] WR @ (0, 16) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> [10000 ps] ACT @ (0, 384) -> [17500 ps] WR @ (0, 16) -> [10000 ps] WR @ (4, 8) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> [17500 ps] WR @ (4, 8) -> [10000 ps] WR @ (0, 8) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10292) -> [10000 ps] ACT @ (0, 11372) -> [17500 ps] WR @ (0, 8) -> [10000 ps] WR @ (4, 8) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> [17500 ps] WR @ (4, 8) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4896) -> [10000 ps] ACT @ (0, 5976) -> [17500 ps] WR @ (0, 0) -> [10000 ps] WR @ (4, 0) -> -[45000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> [17500 ps] WR @ (4, 0) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> -[22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> [17500 ps] WR @ (4, 0) -> [10000 ps] WR @ (0, 0) -> [45000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 580) -> [17500 ps] WR @ (0, 0) -> [ 2500 ps] ACT @ (7, 15884) -> [17500 ps] WR @ (7, 1016) -> [25000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14805) -> [17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12647) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13726) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (3, 12647) -> -[ 2500 ps] PRE @ (4) -> [15000 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 11568) -> [17500 ps] WR @ (3, 1016) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> -[10000 ps] ACT @ (0, 9410) -> [ 7500 ps] WR @ (7, 1016) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 8331) -> -[10000 ps] ACT @ (7, 9409) -> [17500 ps] WR @ (7, 1016) -> [ 2500 ps] ACT @ (4, 7251) -> [42500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> -[17500 ps] WR @ (7, 1016) -> [ 5000 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> -[ 7500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5093) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> -[17500 ps] WR @ (3, 1008) -> [ 5000 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> -[ 7500 ps] WR @ (7, 1008) -> [35000 ps] PRE @ (0) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (0, 2935) -> [10000 ps] ACT @ (7, 4013) -> -[17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1855) -> [ 2500 ps] NOP -> [20000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2934) -> [17500 ps] WR @ (7, 1008) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1855) -> [17500 ps] WR @ (3, 1008) -> -[65000 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 776) -> [10000 ps] ACT @ (3, 776) -> -[10000 ps] ACT @ (0, 16081) -> [ 7500 ps] WR @ (3, 1008) -> [ 2500 ps] ACT @ (7, 16080) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13922) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11764) -> [10000 ps] ACT @ (3, 12843) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10685) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [17500 ps] WR @ (3, 1000) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 7500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8526) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [17500 ps] WR @ (7, 1000) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 7500 ps] WR @ (3, 1000) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 6368) -> [10000 ps] ACT @ (3, 7447) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5289) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 7500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3130) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4209) -> [17500 ps] WR @ (7, 992) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 3130) -> [10000 ps] ACT @ (4, 2051) -> [ 7500 ps] WR @ (3, 992) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 972) -> [17500 ps] WR @ (3, 992) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16276) -> [10000 ps] ACT @ (0, 15198) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14118) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 7500 ps] WR @ (3, 984) -> [35000 ps] PRE @ (4) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (4, 11960) -> [10000 ps] ACT @ (3, 13039) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [17500 ps] WR @ (3, 984) -> [ 5000 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 7500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8722) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [17500 ps] WR @ (7, 984) -> [ 5000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8722) -> [17500 ps] WR @ (3, 984) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [17500 ps] WR @ (3, 976) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [17500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3326) -> [10000 ps] ACT @ (7, 4405) -> -[17500 ps] WR @ (7, 976) -> [10000 ps] WR @ (3, 976) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [17500 ps] WR @ (3, 976) -> -[ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [17500 ps] WR @ (3, 976) -> -[10000 ps] WR @ (7, 976) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14314) -> [10000 ps] ACT @ (7, 15393) -> -[17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> -[10000 ps] ACT @ (3, 13235) -> [17500 ps] WR @ (3, 968) -> [10000 ps] WR @ (7, 968) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> -[17500 ps] WR @ (7, 968) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> -[17500 ps] WR @ (7, 968) -> [10000 ps] WR @ (3, 968) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6759) -> -[10000 ps] ACT @ (3, 7839) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> -[17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> -[17500 ps] WR @ (7, 960) -> [10000 ps] WR @ (3, 960) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1363) -> -[10000 ps] ACT @ (3, 2443) -> [17500 ps] WR @ (3, 960) -> [10000 ps] WR @ (7, 960) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> -[17500 ps] WR @ (7, 960) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> -[17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12351) -> -[10000 ps] ACT @ (3, 13431) -> [17500 ps] WR @ (3, 952) -> [10000 ps] WR @ (7, 952) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> -[17500 ps] WR @ (7, 952) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> -[17500 ps] WR @ (7, 952) -> [10000 ps] WR @ (3, 952) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 6955) -> -[10000 ps] ACT @ (3, 8035) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> -[17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> -[17500 ps] WR @ (7, 944) -> [10000 ps] WR @ (3, 944) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 1559) -> -[10000 ps] ACT @ (3, 2639) -> [17500 ps] WR @ (3, 944) -> [10000 ps] WR @ (7, 944) -> [45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> -[17500 ps] WR @ (7, 944) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> -[17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12547) -> -[10000 ps] ACT @ (3, 13627) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 936) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [17500 ps] WR @ (7, 936) -> [10000 ps] WR @ (3, 936) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9310) -> [17500 ps] WR @ (3, 936) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8231) -> [17500 ps] WR @ (3, 936) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 4993) -> [10000 ps] ACT @ (7, 6072) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 928) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3914) -> [17500 ps] WR @ (3, 928) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2835) -> [17500 ps] WR @ (3, 928) -> [10000 ps] WR @ (7, 928) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 15981) -> [10000 ps] ACT @ (7, 676) -> [17500 ps] WR @ (7, 928) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14902) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13823) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 920) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10585) -> [10000 ps] ACT @ (7, 11664) -> [17500 ps] WR @ (7, 920) -> [10000 ps] WR @ (3, 920) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9506) -> [17500 ps] WR @ (3, 920) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8427) -> [17500 ps] WR @ (3, 920) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 5189) -> [10000 ps] ACT @ (7, 6268) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 912) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4110) -> [17500 ps] WR @ (3, 912) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3031) -> [17500 ps] WR @ (3, 912) -> [10000 ps] WR @ (7, 912) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 16177) -> [10000 ps] ACT @ (7, 872) -> [17500 ps] WR @ (7, 912) -> [10000 ps] WR @ (3, 904) -> [45000 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15098) -> [17500 ps] WR @ (3, 904) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14019) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10781) -> [10000 ps] ACT @ (7, 11860) -> [17500 ps] WR @ (7, 904) -> [10000 ps] WR @ (3, 904) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [17500 ps] WR @ (3, 904) -> [10000 ps] WR @ (7, 904) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 896) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3226) -> [10000 ps] ACT @ (3, 4306) -> [17500 ps] WR @ (3, 896) -> [10000 ps] WR @ (7, 896) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [17500 ps] WR @ (7, 896) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [17500 ps] WR @ (7, 896) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14214) -> [10000 ps] ACT @ (3, 15294) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [17500 ps] WR @ (7, 888) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [17500 ps] WR @ (7, 888) -> [10000 ps] WR @ (3, 888) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8818) -> [10000 ps] ACT @ (3, 9898) -> [17500 ps] WR @ (3, 888) -> [10000 ps] WR @ (7, 888) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 3422) -> [10000 ps] ACT @ (3, 4502) -> [17500 ps] WR @ (3, 880) -> [10000 ps] WR @ (7, 880) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [17500 ps] WR @ (7, 880) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [17500 ps] WR @ (7, 880) -> [10000 ps] WR @ (3, 880) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 14410) -> [10000 ps] ACT @ (3, 15490) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> -[45000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [17500 ps] WR @ (7, 872) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> -[22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [17500 ps] WR @ (7, 872) -> [10000 ps] WR @ (3, 872) -> [35000 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9014) -> [10000 ps] ACT @ (3, 10094) -> [17500 ps] WR @ (3, 872) -> [10000 ps] WR @ (7, 872) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [17500 ps] WR @ (7, 864) -> -[10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3618) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [17500 ps] WR @ (3, 864) -> [10000 ps] WR @ (7, 864) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 1460) -> [10000 ps] ACT @ (7, 2539) -> [17500 ps] WR @ (7, 864) -> -[10000 ps] WR @ (3, 864) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [17500 ps] WR @ (3, 864) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14606) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12448) -> [10000 ps] ACT @ (7, 13527) -> [17500 ps] WR @ (7, 856) -> -[10000 ps] WR @ (3, 856) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [17500 ps] WR @ (3, 856) -> [ 5000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9210) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [17500 ps] WR @ (3, 856) -> [10000 ps] WR @ (7, 856) -> -[35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7052) -> [10000 ps] ACT @ (7, 8131) -> [17500 ps] WR @ (7, 848) -> -[10000 ps] WR @ (3, 848) -> [ 5000 ps] NOP -> [40000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [17500 ps] WR @ (3, 848) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [17500 ps] WR @ (3, 848) -> [65000 ps] PRE @ (0) -> [30000 ps] REF -> -[360000 ps] NOP -> [17500 ps] ACT @ (7, 3814) -> [17500 ps] WR @ (7, 848) -> [ 2500 ps] ACT @ (3, 1656) -> [42500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2735) -> [17500 ps] WR @ (7, 848) -> [10000 ps] WR @ (3, 848) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> -[17500 ps] WR @ (3, 848) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14802) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> -[17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 12644) -> -[10000 ps] ACT @ (7, 13723) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 840) -> [45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> -[17500 ps] WR @ (3, 840) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9406) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> -[17500 ps] WR @ (3, 840) -> [10000 ps] WR @ (7, 840) -> [35000 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7248) -> -[10000 ps] ACT @ (7, 8327) -> [17500 ps] WR @ (7, 840) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 832) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4010) -> [17500 ps] WR @ (7, 832) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 2931) -> [17500 ps] WR @ (7, 832) -> [10000 ps] WR @ (3, 832) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 16077) -> [10000 ps] ACT @ (3, 773) -> [17500 ps] WR @ (3, 832) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14998) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13919) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 824) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 10681) -> [10000 ps] ACT @ (3, 11761) -> [17500 ps] WR @ (3, 824) -> [10000 ps] WR @ (7, 824) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9602) -> [17500 ps] WR @ (7, 824) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8523) -> [17500 ps] WR @ (7, 824) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 5285) -> [10000 ps] ACT @ (3, 6365) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 816) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4206) -> [17500 ps] WR @ (7, 816) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3127) -> [17500 ps] WR @ (7, 816) -> [10000 ps] WR @ (3, 816) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 16273) -> [10000 ps] ACT @ (3, 969) -> [17500 ps] WR @ (3, 816) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 15194) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14115) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 808) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 10877) -> [10000 ps] ACT @ (3, 11957) -> [17500 ps] WR @ (3, 808) -> [10000 ps] WR @ (7, 808) -> [45000 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9798) -> [17500 ps] WR @ (7, 808) -> [ 5000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [22500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 8719) -> [17500 ps] WR @ (7, 808) -> [10000 ps] WR @ (3, 800) -> [35000 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 5481) -> [10000 ps] ACT @ (3, 6561) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> [10000 ps] ACT @ (7, 4402) -> [17500 ps] WR @ (7, 800) -> [10000 ps] WR @ (3, 800) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> [17500 ps] WR @ (3, 800) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> [17500 ps] WR @ (3, 800) -> [10000 ps] WR @ (7, 800) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14311) -> [10000 ps] ACT @ (7, 15390) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> [17500 ps] WR @ (3, 792) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> [17500 ps] WR @ (3, 792) -> [10000 ps] WR @ (7, 792) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8915) -> [10000 ps] ACT @ (7, 9994) -> [17500 ps] WR @ (7, 792) -> [10000 ps] WR @ (3, 792) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3519) -> [10000 ps] ACT @ (7, 4598) -> [17500 ps] WR @ (7, 784) -> [10000 ps] WR @ (3, 784) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> [17500 ps] WR @ (3, 784) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> [17500 ps] WR @ (3, 784) -> [10000 ps] WR @ (7, 784) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 14507) -> [10000 ps] ACT @ (7, 15586) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> [17500 ps] WR @ (3, 776) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> [17500 ps] WR @ (3, 776) -> [10000 ps] WR @ (7, 776) -> [35000 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9111) -> [10000 ps] ACT @ (7, 10190) -> [17500 ps] WR @ (7, 776) -> [10000 ps] WR @ (3, 776) -> -[45000 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8032) -> [17500 ps] WR @ (3, 768) -> [ 5000 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> -[22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6953) -> [17500 ps] WR @ (3, 768) -> [ 2500 ps] ACT @ (4, 2852) -> [ 7500 ps] WR @ (7, 768) -> -[ 2500 ps] ACT @ (0, 1773) -> [35000 ps] RD @ (4, 960) -> [10000 ps] RD @ (0, 960) -> [ 7500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 15998) -> [10000 ps] ACT @ (0, 694) -> [15000 ps] RD @ (0, 960) -> [10000 ps] RD @ (4, 952) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14919) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12761) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13840) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 952) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11682) -> [10000 ps] ACT @ (4, 10602) -> [ 5000 ps] RD @ (0, 952) -> [10000 ps] RD @ (4, 952) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9523) -> [15000 ps] RD @ (4, 952) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7365) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8444) -> [15000 ps] RD @ (4, 952) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6286) -> [10000 ps] ACT @ (4, 5206) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 944) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4127) -> [15000 ps] RD @ (4, 944) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1969) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3048) -> [15000 ps] RD @ (4, 944) -> [10000 ps] RD @ (0, 944) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 890) -> [10000 ps] ACT @ (4, 16194) -> [ 5000 ps] RD @ (0, 944) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15115) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12957) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14036) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 936) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11878) -> [10000 ps] ACT @ (4, 10798) -> [ 5000 ps] RD @ (0, 936) -> [10000 ps] RD @ (4, 936) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9719) -> [15000 ps] RD @ (4, 936) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7561) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8640) -> [15000 ps] RD @ (4, 936) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6482) -> [10000 ps] ACT @ (4, 5402) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4323) -> [15000 ps] RD @ (4, 928) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2165) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3244) -> [15000 ps] RD @ (4, 928) -> [10000 ps] RD @ (0, 928) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1086) -> [10000 ps] ACT @ (4, 6) -> [ 5000 ps] RD @ (0, 928) -> [10000 ps] RD @ (4, 928) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14232) -> [10000 ps] ACT @ (4, 15311) -> [15000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13153) -> [15000 ps] RD @ (0, 920) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10994) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12074) -> [15000 ps] RD @ (0, 920) -> [10000 ps] RD @ (4, 920) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9915) -> [10000 ps] ACT @ (0, 8836) -> [ 5000 ps] RD @ (4, 920) -> [10000 ps] RD @ (0, 920) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7757) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5598) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6678) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4519) -> [10000 ps] ACT @ (0, 3440) -> [ 5000 ps] RD @ (4, 912) -> [10000 ps] RD @ (0, 912) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2361) -> [15000 ps] RD @ (0, 912) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 202) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1282) -> [15000 ps] RD @ (0, 912) -> [10000 ps] RD @ (4, 912) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15507) -> [10000 ps] ACT @ (0, 14428) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13349) -> [15000 ps] RD @ (0, 904) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11190) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12270) -> [15000 ps] RD @ (0, 904) -> [10000 ps] RD @ (4, 904) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10111) -> [10000 ps] ACT @ (0, 9032) -> [ 5000 ps] RD @ (4, 904) -> [10000 ps] RD @ (0, 904) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7953) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5794) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6874) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4715) -> [10000 ps] ACT @ (0, 3636) -> [ 5000 ps] RD @ (4, 896) -> [10000 ps] RD @ (0, 896) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2557) -> [15000 ps] RD @ (0, 896) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 398) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1478) -> [15000 ps] RD @ (0, 896) -> [10000 ps] RD @ (4, 896) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15703) -> [10000 ps] ACT @ (0, 14624) -> [ 5000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12465) -> [10000 ps] ACT @ (0, 13545) -> [15000 ps] RD @ (0, 888) -> -[10000 ps] RD @ (4, 888) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11386) -> [15000 ps] RD @ (4, 888) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9228) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10307) -> [15000 ps] RD @ (4, 888) -> [10000 ps] RD @ (0, 888) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8149) -> [10000 ps] ACT @ (4, 7069) -> [ 5000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5990) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3832) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4911) -> [15000 ps] RD @ (4, 880) -> [10000 ps] RD @ (0, 880) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2753) -> [10000 ps] ACT @ (4, 1673) -> [ 5000 ps] RD @ (0, 880) -> -[10000 ps] RD @ (4, 880) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 594) -> [15000 ps] RD @ (4, 880) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14820) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15899) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13741) -> [10000 ps] ACT @ (4, 12661) -> [ 5000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (4, 872) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11582) -> [15000 ps] RD @ (4, 872) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9424) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10503) -> [15000 ps] RD @ (4, 872) -> [10000 ps] RD @ (0, 872) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8345) -> [10000 ps] ACT @ (4, 7265) -> [ 5000 ps] RD @ (0, 872) -> -[10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6186) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4028) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5107) -> [15000 ps] RD @ (4, 864) -> [10000 ps] RD @ (0, 864) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2949) -> [10000 ps] ACT @ (4, 1869) -> [ 5000 ps] RD @ (0, 864) -> -[10000 ps] RD @ (4, 864) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 790) -> [15000 ps] RD @ (4, 864) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15016) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16095) -> [15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13937) -> [10000 ps] ACT @ (4, 12857) -> [ 5000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (4, 856) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10699) -> [10000 ps] ACT @ (4, 11778) -> -[15000 ps] RD @ (4, 856) -> [10000 ps] RD @ (0, 856) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9620) -> [15000 ps] RD @ (0, 856) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7461) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8541) -> [15000 ps] RD @ (0, 856) -> -[10000 ps] RD @ (4, 848) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6382) -> [10000 ps] ACT @ (0, 5303) -> -[ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 848) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4224) -> [15000 ps] RD @ (0, 848) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2065) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3145) -> [15000 ps] RD @ (0, 848) -> -[10000 ps] RD @ (4, 848) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 986) -> -[10000 ps] ACT @ (0, 16291) -> [ 5000 ps] RD @ (4, 848) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15212) -> -[15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13053) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14133) -> -[15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 840) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11974) -> -[10000 ps] ACT @ (0, 10895) -> [ 5000 ps] RD @ (4, 840) -> [10000 ps] RD @ (0, 840) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9816) -> -[15000 ps] RD @ (0, 840) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7657) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8737) -> -[15000 ps] RD @ (0, 840) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6578) -> -[10000 ps] ACT @ (0, 5499) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4420) -> -[15000 ps] RD @ (0, 832) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2261) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3341) -> -[15000 ps] RD @ (0, 832) -> [10000 ps] RD @ (4, 832) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1182) -> -[10000 ps] ACT @ (0, 103) -> [ 5000 ps] RD @ (4, 832) -> [10000 ps] RD @ (0, 832) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15408) -> -[15000 ps] RD @ (0, 824) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13249) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14329) -> -[15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12170) -> -[10000 ps] ACT @ (0, 11091) -> [ 5000 ps] RD @ (4, 824) -> [10000 ps] RD @ (0, 824) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 8932) -> [10000 ps] ACT @ (0, 10012) -> [15000 ps] RD @ (0, 824) -> [10000 ps] RD @ (4, 824) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7853) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5695) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6774) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4616) -> [10000 ps] ACT @ (4, 3536) -> [ 5000 ps] RD @ (0, 816) -> [10000 ps] RD @ (4, 816) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2457) -> [15000 ps] RD @ (4, 816) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 299) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1378) -> [15000 ps] RD @ (4, 816) -> [10000 ps] RD @ (0, 816) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15604) -> [10000 ps] ACT @ (4, 14524) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13445) -> [15000 ps] RD @ (4, 808) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11287) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12366) -> [15000 ps] RD @ (4, 808) -> [10000 ps] RD @ (0, 808) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10208) -> [10000 ps] ACT @ (4, 9128) -> [ 5000 ps] RD @ (0, 808) -> [10000 ps] RD @ (4, 808) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8049) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5891) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 6970) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 4812) -> [10000 ps] ACT @ (4, 3732) -> [ 5000 ps] RD @ (0, 800) -> [10000 ps] RD @ (4, 800) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2653) -> [15000 ps] RD @ (4, 800) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 495) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1574) -> [15000 ps] RD @ (4, 800) -> [10000 ps] RD @ (0, 800) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 15800) -> [10000 ps] ACT @ (4, 14720) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13641) -> [15000 ps] RD @ (4, 792) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11483) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 12562) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 792) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10404) -> [10000 ps] ACT @ (4, 9324) -> [ 5000 ps] RD @ (0, 792) -> [10000 ps] RD @ (4, 792) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7166) -> [10000 ps] ACT @ (4, 8245) -> [15000 ps] RD @ (4, 792) -> [10000 ps] RD @ (0, 784) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6087) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3928) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5008) -> [15000 ps] RD @ (0, 784) -> [10000 ps] RD @ (4, 784) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2849) -> [10000 ps] ACT @ (0, 1770) -> [ 5000 ps] RD @ (4, 784) -> [10000 ps] RD @ (0, 784) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 691) -> [15000 ps] RD @ (0, 784) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14916) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15996) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13837) -> [10000 ps] ACT @ (0, 12758) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 776) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11679) -> [15000 ps] RD @ (0, 776) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9520) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10600) -> [15000 ps] RD @ (0, 776) -> [10000 ps] RD @ (4, 776) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8441) -> [10000 ps] ACT @ (0, 7362) -> [ 5000 ps] RD @ (4, 776) -> [10000 ps] RD @ (0, 768) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6283) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4124) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5204) -> [15000 ps] RD @ (0, 768) -> [10000 ps] RD @ (4, 768) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3045) -> [10000 ps] ACT @ (0, 1966) -> [ 5000 ps] RD @ (4, 768) -> [10000 ps] RD @ (0, 768) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 887) -> [15000 ps] RD @ (0, 768) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15112) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16192) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14033) -> [10000 ps] ACT @ (0, 12954) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 760) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11875) -> [15000 ps] RD @ (0, 760) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9716) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10796) -> [15000 ps] RD @ (0, 760) -> [10000 ps] RD @ (4, 760) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8637) -> [10000 ps] ACT @ (0, 7558) -> [ 5000 ps] RD @ (4, 760) -> [10000 ps] RD @ (0, 752) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5399) -> [10000 ps] ACT @ (0, 6479) -> [15000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (4, 752) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4320) -> [15000 ps] RD @ (4, 752) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2162) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3241) -> [15000 ps] RD @ (4, 752) -> [10000 ps] RD @ (0, 752) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1083) -> [10000 ps] ACT @ (4, 3) -> [ 5000 ps] RD @ (0, 752) -> -[10000 ps] RD @ (4, 752) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15308) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13150) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14229) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 744) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12071) -> [10000 ps] ACT @ (4, 10991) -> [ 5000 ps] RD @ (0, 744) -> -[10000 ps] RD @ (4, 744) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9912) -> [15000 ps] RD @ (4, 744) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7754) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8833) -> [15000 ps] RD @ (4, 744) -> [10000 ps] RD @ (0, 736) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6675) -> [10000 ps] ACT @ (4, 5595) -> [ 5000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4516) -> [15000 ps] RD @ (4, 736) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2358) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3437) -> [15000 ps] RD @ (4, 736) -> [10000 ps] RD @ (0, 736) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1279) -> [10000 ps] ACT @ (4, 199) -> [ 5000 ps] RD @ (0, 736) -> -[10000 ps] RD @ (4, 736) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15504) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13346) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14425) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 728) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12267) -> [10000 ps] ACT @ (4, 11187) -> [ 5000 ps] RD @ (0, 728) -> -[10000 ps] RD @ (4, 728) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10108) -> [15000 ps] RD @ (4, 728) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 7950) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9029) -> [15000 ps] RD @ (4, 728) -> [10000 ps] RD @ (0, 720) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 6871) -> [10000 ps] ACT @ (4, 5791) -> [ 5000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3633) -> [10000 ps] ACT @ (4, 4712) -> -[15000 ps] RD @ (4, 720) -> [10000 ps] RD @ (0, 720) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2554) -> [15000 ps] RD @ (0, 720) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 395) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1475) -> [15000 ps] RD @ (0, 720) -> -[10000 ps] RD @ (4, 720) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15700) -> [10000 ps] ACT @ (0, 14621) -> -[ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13542) -> [15000 ps] RD @ (0, 712) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11383) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12463) -> [15000 ps] RD @ (0, 712) -> -[10000 ps] RD @ (4, 712) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10304) -> [10000 ps] ACT @ (0, 9225) -> -[ 5000 ps] RD @ (4, 712) -> [10000 ps] RD @ (0, 712) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8146) -> [15000 ps] RD @ (0, 704) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5987) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7067) -> [15000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4908) -> [10000 ps] ACT @ (0, 3829) -> -[ 5000 ps] RD @ (4, 704) -> [10000 ps] RD @ (0, 704) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2750) -> [15000 ps] RD @ (0, 704) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 591) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1671) -> [15000 ps] RD @ (0, 704) -> -[10000 ps] RD @ (4, 704) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15896) -> [10000 ps] ACT @ (0, 14817) -> -[ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13738) -> [15000 ps] RD @ (0, 696) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11579) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12659) -> [15000 ps] RD @ (0, 696) -> -[10000 ps] RD @ (4, 696) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10500) -> [10000 ps] ACT @ (0, 9421) -> -[ 5000 ps] RD @ (4, 696) -> [10000 ps] RD @ (0, 696) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8342) -> [15000 ps] RD @ (0, 696) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6183) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7263) -> [15000 ps] RD @ (0, 688) -> -[10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5104) -> [10000 ps] ACT @ (0, 4025) -> -[ 5000 ps] RD @ (4, 688) -> [10000 ps] RD @ (0, 688) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1866) -> -[10000 ps] ACT @ (0, 2946) -> [15000 ps] RD @ (0, 688) -> [10000 ps] RD @ (4, 688) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 787) -> -[15000 ps] RD @ (4, 688) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15013) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16092) -> -[15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 13934) -> -[10000 ps] ACT @ (4, 12854) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 680) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11775) -> -[15000 ps] RD @ (4, 680) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9617) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10696) -> -[15000 ps] RD @ (4, 680) -> [10000 ps] RD @ (0, 680) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8538) -> -[10000 ps] ACT @ (4, 7458) -> [ 5000 ps] RD @ (0, 680) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6379) -> -[15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4221) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5300) -> -[15000 ps] RD @ (4, 672) -> [10000 ps] RD @ (0, 672) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3142) -> -[10000 ps] ACT @ (4, 2062) -> [ 5000 ps] RD @ (0, 672) -> [10000 ps] RD @ (4, 672) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 983) -> -[15000 ps] RD @ (4, 672) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15209) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16288) -> -[15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14130) -> -[10000 ps] ACT @ (4, 13050) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 664) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11971) -> -[15000 ps] RD @ (4, 664) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9813) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10892) -> -[15000 ps] RD @ (4, 664) -> [10000 ps] RD @ (0, 664) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8734) -> -[10000 ps] ACT @ (4, 7654) -> [ 5000 ps] RD @ (0, 664) -> [10000 ps] RD @ (4, 656) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6575) -> -[15000 ps] RD @ (4, 656) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4417) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5496) -> -[15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3338) -> -[10000 ps] ACT @ (4, 2258) -> [ 5000 ps] RD @ (0, 656) -> [10000 ps] RD @ (4, 656) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 100) -> [10000 ps] ACT @ (4, 1179) -> [15000 ps] RD @ (4, 656) -> [10000 ps] RD @ (0, 656) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15405) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13246) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14326) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 648) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12167) -> [10000 ps] ACT @ (0, 11088) -> [ 5000 ps] RD @ (4, 648) -> [10000 ps] RD @ (0, 648) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10009) -> [15000 ps] RD @ (0, 648) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7850) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8930) -> [15000 ps] RD @ (0, 648) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6771) -> [10000 ps] ACT @ (0, 5692) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4613) -> [15000 ps] RD @ (0, 640) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2454) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3534) -> [15000 ps] RD @ (0, 640) -> [10000 ps] RD @ (4, 640) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1375) -> [10000 ps] ACT @ (0, 296) -> [ 5000 ps] RD @ (4, 640) -> [10000 ps] RD @ (0, 640) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15601) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13442) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 14522) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 632) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12363) -> [10000 ps] ACT @ (0, 11284) -> [ 5000 ps] RD @ (4, 632) -> [10000 ps] RD @ (0, 632) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10205) -> [15000 ps] RD @ (0, 632) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8046) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9126) -> [15000 ps] RD @ (0, 632) -> [10000 ps] RD @ (4, 624) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6967) -> [10000 ps] ACT @ (0, 5888) -> [ 5000 ps] RD @ (4, 624) -> [ 7500 ps] NOP -> [ 2500 ps] RD @ (0, 624) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4809) -> [15000 ps] RD @ (0, 624) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3730) -> -[15000 ps] RD @ (0, 624) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> [17500 ps] ACT @ (4, 2650) -> -[15000 ps] RD @ (4, 624) -> [ 5000 ps] ACT @ (0, 492) -> [22500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1571) -> [15000 ps] RD @ (4, 624) -> -[10000 ps] RD @ (0, 624) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15797) -> [10000 ps] ACT @ (4, 14717) -> -[ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13638) -> [15000 ps] RD @ (4, 616) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11480) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12559) -> [15000 ps] RD @ (4, 616) -> -[10000 ps] RD @ (0, 616) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10401) -> [10000 ps] ACT @ (4, 9321) -> -[ 5000 ps] RD @ (0, 616) -> [10000 ps] RD @ (4, 616) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8242) -> [15000 ps] RD @ (4, 616) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6084) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7163) -> [15000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5005) -> [10000 ps] ACT @ (4, 3925) -> -[ 5000 ps] RD @ (0, 608) -> [10000 ps] RD @ (4, 608) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2846) -> [15000 ps] RD @ (4, 608) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 688) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1767) -> [15000 ps] RD @ (4, 608) -> -[10000 ps] RD @ (0, 608) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15993) -> [10000 ps] ACT @ (4, 14913) -> -[ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13834) -> [15000 ps] RD @ (4, 600) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11676) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12755) -> [15000 ps] RD @ (4, 600) -> -[10000 ps] RD @ (0, 600) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10597) -> [10000 ps] ACT @ (4, 9517) -> -[ 5000 ps] RD @ (0, 600) -> [10000 ps] RD @ (4, 600) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8438) -> [15000 ps] RD @ (4, 600) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6280) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7359) -> [15000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5201) -> [10000 ps] ACT @ (4, 4121) -> -[ 5000 ps] RD @ (0, 592) -> [10000 ps] RD @ (4, 592) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3042) -> [15000 ps] RD @ (4, 592) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 884) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1963) -> [15000 ps] RD @ (4, 592) -> -[10000 ps] RD @ (0, 592) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16189) -> [10000 ps] ACT @ (4, 15109) -> -[ 5000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12951) -> -[10000 ps] ACT @ (4, 14030) -> [15000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 584) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11872) -> -[15000 ps] RD @ (0, 584) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9713) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10793) -> -[15000 ps] RD @ (0, 584) -> [10000 ps] RD @ (4, 584) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8634) -> -[10000 ps] ACT @ (0, 7555) -> [ 5000 ps] RD @ (4, 584) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6476) -> -[15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4317) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5397) -> -[15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 576) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3238) -> -[10000 ps] ACT @ (0, 2159) -> [ 5000 ps] RD @ (4, 576) -> [10000 ps] RD @ (0, 576) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1080) -> -[15000 ps] RD @ (0, 576) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15305) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1) -> -[15000 ps] RD @ (0, 576) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14226) -> -[10000 ps] ACT @ (0, 13147) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 568) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12068) -> -[15000 ps] RD @ (0, 568) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9909) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10989) -> -[15000 ps] RD @ (0, 568) -> [10000 ps] RD @ (4, 568) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 8830) -> -[10000 ps] ACT @ (0, 7751) -> [ 5000 ps] RD @ (4, 568) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6672) -> -[15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4513) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5593) -> -[15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 560) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3434) -> -[10000 ps] ACT @ (0, 2355) -> [ 5000 ps] RD @ (4, 560) -> [10000 ps] RD @ (0, 560) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1276) -> -[15000 ps] RD @ (0, 560) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15501) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 197) -> -[15000 ps] RD @ (0, 560) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14422) -> -[10000 ps] ACT @ (0, 13343) -> [ 5000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 552) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 11184) -> [10000 ps] ACT @ (0, 12264) -> [15000 ps] RD @ (0, 552) -> [10000 ps] RD @ (4, 552) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10105) -> [15000 ps] RD @ (4, 552) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7947) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9026) -> [15000 ps] RD @ (4, 552) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 6868) -> [10000 ps] ACT @ (4, 5788) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4709) -> [15000 ps] RD @ (4, 544) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2551) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3630) -> [15000 ps] RD @ (4, 544) -> [10000 ps] RD @ (0, 544) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1472) -> [10000 ps] ACT @ (4, 392) -> [ 5000 ps] RD @ (0, 544) -> [10000 ps] RD @ (4, 544) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15697) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13539) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14618) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 536) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12460) -> [10000 ps] ACT @ (4, 11380) -> [ 5000 ps] RD @ (0, 536) -> [10000 ps] RD @ (4, 536) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10301) -> [15000 ps] RD @ (4, 536) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8143) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9222) -> [15000 ps] RD @ (4, 536) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7064) -> [10000 ps] ACT @ (4, 5984) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4905) -> [15000 ps] RD @ (4, 528) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2747) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3826) -> [15000 ps] RD @ (4, 528) -> [10000 ps] RD @ (0, 528) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 1668) -> [10000 ps] ACT @ (4, 588) -> [ 5000 ps] RD @ (0, 528) -> [10000 ps] RD @ (4, 528) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15893) -> [15000 ps] RD @ (4, 520) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13735) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14814) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 12656) -> [10000 ps] ACT @ (4, 11576) -> [ 5000 ps] RD @ (0, 520) -> [10000 ps] RD @ (4, 520) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9418) -> [10000 ps] ACT @ (4, 10497) -> [15000 ps] RD @ (4, 520) -> [10000 ps] RD @ (0, 520) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8339) -> [15000 ps] RD @ (0, 520) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6180) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7260) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5101) -> [10000 ps] ACT @ (0, 4022) -> [ 5000 ps] RD @ (4, 512) -> [10000 ps] RD @ (0, 512) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2943) -> [15000 ps] RD @ (0, 512) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 784) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1864) -> [15000 ps] RD @ (0, 512) -> [10000 ps] RD @ (4, 512) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16089) -> [10000 ps] ACT @ (0, 15010) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13931) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11772) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12852) -> [15000 ps] RD @ (0, 504) -> [10000 ps] RD @ (4, 504) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10693) -> [10000 ps] ACT @ (0, 9614) -> [ 5000 ps] RD @ (4, 504) -> [10000 ps] RD @ (0, 504) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8535) -> [15000 ps] RD @ (0, 504) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6376) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7456) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5297) -> [10000 ps] ACT @ (0, 4218) -> [ 5000 ps] RD @ (4, 496) -> [10000 ps] RD @ (0, 496) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3139) -> [15000 ps] RD @ (0, 496) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 980) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2060) -> [15000 ps] RD @ (0, 496) -> [10000 ps] RD @ (4, 496) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 16285) -> [10000 ps] ACT @ (0, 15206) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14127) -> [15000 ps] RD @ (0, 488) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11968) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13048) -> [15000 ps] RD @ (0, 488) -> [10000 ps] RD @ (4, 488) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10889) -> [10000 ps] ACT @ (0, 9810) -> [ 5000 ps] RD @ (4, 488) -> [10000 ps] RD @ (0, 488) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7651) -> [10000 ps] ACT @ (0, 8731) -> [15000 ps] RD @ (0, 488) -> -[10000 ps] RD @ (4, 480) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6572) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4414) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5493) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 480) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3335) -> [10000 ps] ACT @ (4, 2255) -> [ 5000 ps] RD @ (0, 480) -> -[10000 ps] RD @ (4, 480) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1176) -> [15000 ps] RD @ (4, 480) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15402) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 97) -> [15000 ps] RD @ (4, 480) -> [10000 ps] RD @ (0, 472) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14323) -> [10000 ps] ACT @ (4, 13243) -> [ 5000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (4, 472) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12164) -> [15000 ps] RD @ (4, 472) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10006) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11085) -> [15000 ps] RD @ (4, 472) -> [10000 ps] RD @ (0, 472) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8927) -> [10000 ps] ACT @ (4, 7847) -> [ 5000 ps] RD @ (0, 472) -> -[10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6768) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4610) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5689) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 464) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3531) -> [10000 ps] ACT @ (4, 2451) -> [ 5000 ps] RD @ (0, 464) -> -[10000 ps] RD @ (4, 464) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1372) -> [15000 ps] RD @ (4, 464) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15598) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 293) -> [15000 ps] RD @ (4, 464) -> [10000 ps] RD @ (0, 456) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14519) -> [10000 ps] ACT @ (4, 13439) -> [ 5000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (4, 456) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12360) -> [15000 ps] RD @ (4, 456) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10202) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11281) -> [15000 ps] RD @ (4, 456) -> [10000 ps] RD @ (0, 456) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9123) -> [10000 ps] ACT @ (4, 8043) -> [ 5000 ps] RD @ (0, 456) -> -[10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5885) -> [10000 ps] ACT @ (4, 6964) -> -[15000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4806) -> [15000 ps] RD @ (0, 448) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2647) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3727) -> [15000 ps] RD @ (0, 448) -> -[10000 ps] RD @ (4, 448) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1568) -> [10000 ps] ACT @ (0, 489) -> -[ 5000 ps] RD @ (4, 448) -> [10000 ps] RD @ (0, 448) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15794) -> [15000 ps] RD @ (0, 440) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13635) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14715) -> [15000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12556) -> [10000 ps] ACT @ (0, 11477) -> -[ 5000 ps] RD @ (4, 440) -> [10000 ps] RD @ (0, 440) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10398) -> [15000 ps] RD @ (0, 440) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8239) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9319) -> [15000 ps] RD @ (0, 440) -> -[10000 ps] RD @ (4, 440) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7160) -> [10000 ps] ACT @ (0, 6081) -> -[ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5002) -> [15000 ps] RD @ (0, 432) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2843) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3923) -> [15000 ps] RD @ (0, 432) -> -[10000 ps] RD @ (4, 432) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 1764) -> [10000 ps] ACT @ (0, 685) -> -[ 5000 ps] RD @ (4, 432) -> [10000 ps] RD @ (0, 432) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15990) -> [15000 ps] RD @ (0, 424) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13831) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14911) -> [15000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 12752) -> [10000 ps] ACT @ (0, 11673) -> -[ 5000 ps] RD @ (4, 424) -> [10000 ps] RD @ (0, 424) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10594) -> [15000 ps] RD @ (0, 424) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8435) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9515) -> [15000 ps] RD @ (0, 424) -> -[10000 ps] RD @ (4, 424) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7356) -> [10000 ps] ACT @ (0, 6277) -> -[ 5000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4118) -> -[10000 ps] ACT @ (0, 5198) -> [15000 ps] RD @ (0, 416) -> [10000 ps] RD @ (4, 416) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3039) -> -[15000 ps] RD @ (4, 416) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 881) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1960) -> -[15000 ps] RD @ (4, 416) -> [10000 ps] RD @ (0, 416) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 16186) -> -[10000 ps] ACT @ (4, 15106) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14027) -> -[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11869) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12948) -> -[15000 ps] RD @ (4, 408) -> [10000 ps] RD @ (0, 408) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 10790) -> -[10000 ps] ACT @ (4, 9710) -> [ 5000 ps] RD @ (0, 408) -> [10000 ps] RD @ (4, 408) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8631) -> -[15000 ps] RD @ (4, 408) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6473) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7552) -> -[15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 5394) -> [10000 ps] ACT @ (4, 4314) -> [ 5000 ps] RD @ (0, 400) -> [10000 ps] RD @ (4, 400) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 3235) -> [15000 ps] RD @ (4, 400) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1077) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 2156) -> [15000 ps] RD @ (4, 400) -> [10000 ps] RD @ (0, 400) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 16382) -> [10000 ps] ACT @ (4, 15302) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 14223) -> [15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12065) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13144) -> [15000 ps] RD @ (4, 392) -> [10000 ps] RD @ (0, 392) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 10986) -> [10000 ps] ACT @ (4, 9906) -> [ 5000 ps] RD @ (0, 392) -> [10000 ps] RD @ (4, 392) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8827) -> [15000 ps] RD @ (4, 392) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6669) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 7748) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 5590) -> [10000 ps] ACT @ (4, 4510) -> [ 5000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 384) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2352) -> [10000 ps] ACT @ (4, 3431) -> [15000 ps] RD @ (4, 384) -> [10000 ps] RD @ (0, 384) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1273) -> [15000 ps] RD @ (0, 384) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15498) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 194) -> [15000 ps] RD @ (0, 384) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14419) -> [10000 ps] ACT @ (0, 13340) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 376) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12261) -> [15000 ps] RD @ (0, 376) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10102) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11182) -> [15000 ps] RD @ (0, 376) -> [10000 ps] RD @ (4, 376) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9023) -> [10000 ps] ACT @ (0, 7944) -> [ 5000 ps] RD @ (4, 376) -> [10000 ps] RD @ (0, 368) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6865) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4706) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5786) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 368) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3627) -> [10000 ps] ACT @ (0, 2548) -> [ 5000 ps] RD @ (4, 368) -> [10000 ps] RD @ (0, 368) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1469) -> [15000 ps] RD @ (0, 368) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15694) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 390) -> [15000 ps] RD @ (0, 368) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14615) -> [10000 ps] ACT @ (0, 13536) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 360) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12457) -> [15000 ps] RD @ (0, 360) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10298) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11378) -> [15000 ps] RD @ (0, 360) -> [10000 ps] RD @ (4, 360) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9219) -> [10000 ps] ACT @ (0, 8140) -> [ 5000 ps] RD @ (4, 360) -> [10000 ps] RD @ (0, 352) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7061) -> [15000 ps] RD @ (0, 352) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4902) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5982) -> [15000 ps] RD @ (0, 352) -> [10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3823) -> [10000 ps] ACT @ (0, 2744) -> [ 5000 ps] RD @ (4, 352) -> [10000 ps] RD @ (0, 352) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 585) -> [10000 ps] ACT @ (0, 1665) -> [15000 ps] RD @ (0, 352) -> -[10000 ps] RD @ (4, 352) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15890) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13732) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14811) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12653) -> [10000 ps] ACT @ (4, 11573) -> [ 5000 ps] RD @ (0, 344) -> -[10000 ps] RD @ (4, 344) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10494) -> [15000 ps] RD @ (4, 344) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8336) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9415) -> [15000 ps] RD @ (4, 344) -> [10000 ps] RD @ (0, 344) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7257) -> [10000 ps] ACT @ (4, 6177) -> [ 5000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5098) -> [15000 ps] RD @ (4, 336) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 2940) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4019) -> [15000 ps] RD @ (4, 336) -> [10000 ps] RD @ (0, 336) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1861) -> [10000 ps] ACT @ (4, 781) -> [ 5000 ps] RD @ (0, 336) -> -[10000 ps] RD @ (4, 336) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16086) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 13928) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15007) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 12849) -> [10000 ps] ACT @ (4, 11769) -> [ 5000 ps] RD @ (0, 328) -> -[10000 ps] RD @ (4, 328) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10690) -> [15000 ps] RD @ (4, 328) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 8532) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9611) -> [15000 ps] RD @ (4, 328) -> [10000 ps] RD @ (0, 328) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 7453) -> [10000 ps] ACT @ (4, 6373) -> [ 5000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (4, 320) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5294) -> [15000 ps] RD @ (4, 320) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 3136) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 4215) -> [15000 ps] RD @ (4, 320) -> [10000 ps] RD @ (0, 320) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 2057) -> [10000 ps] ACT @ (4, 977) -> [ 5000 ps] RD @ (0, 320) -> -[10000 ps] RD @ (4, 320) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15203) -> [10000 ps] ACT @ (4, 16282) -> -[15000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14124) -> [15000 ps] RD @ (0, 312) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11965) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13045) -> [15000 ps] RD @ (0, 312) -> -[10000 ps] RD @ (4, 312) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 10886) -> [10000 ps] ACT @ (0, 9807) -> -[ 5000 ps] RD @ (4, 312) -> [10000 ps] RD @ (0, 312) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8728) -> [15000 ps] RD @ (0, 312) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6569) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7649) -> [15000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5490) -> [10000 ps] ACT @ (0, 4411) -> -[ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 304) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3332) -> [15000 ps] RD @ (0, 304) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1173) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2253) -> [15000 ps] RD @ (0, 304) -> -[10000 ps] RD @ (4, 304) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 94) -> [10000 ps] ACT @ (0, 15399) -> -[ 5000 ps] RD @ (4, 304) -> [10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14320) -> [15000 ps] RD @ (0, 296) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12161) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13241) -> [15000 ps] RD @ (0, 296) -> -[10000 ps] RD @ (4, 296) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11082) -> [10000 ps] ACT @ (0, 10003) -> -[ 5000 ps] RD @ (4, 296) -> [10000 ps] RD @ (0, 296) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8924) -> [15000 ps] RD @ (0, 296) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6765) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7845) -> [15000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5686) -> [10000 ps] ACT @ (0, 4607) -> -[ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 288) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3528) -> [15000 ps] RD @ (0, 288) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1369) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2449) -> [15000 ps] RD @ (0, 288) -> -[10000 ps] RD @ (4, 288) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 290) -> [10000 ps] ACT @ (0, 15595) -> -[ 5000 ps] RD @ (4, 288) -> [10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13436) -> -[10000 ps] ACT @ (0, 14516) -> [15000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 280) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12357) -> -[15000 ps] RD @ (4, 280) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10199) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11278) -> -[15000 ps] RD @ (4, 280) -> [10000 ps] RD @ (0, 280) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9120) -> -[10000 ps] ACT @ (4, 8040) -> [ 5000 ps] RD @ (0, 280) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6961) -> -[15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4803) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5882) -> -[15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 272) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3724) -> -[10000 ps] ACT @ (4, 2644) -> [ 5000 ps] RD @ (0, 272) -> [10000 ps] RD @ (4, 272) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1565) -> -[15000 ps] RD @ (4, 272) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15791) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 486) -> -[15000 ps] RD @ (4, 272) -> [10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14712) -> -[10000 ps] ACT @ (4, 13632) -> [ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12553) -> -[15000 ps] RD @ (4, 264) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10395) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11474) -> -[15000 ps] RD @ (4, 264) -> [10000 ps] RD @ (0, 264) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9316) -> -[10000 ps] ACT @ (4, 8236) -> [ 5000 ps] RD @ (0, 264) -> [10000 ps] RD @ (4, 264) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7157) -> -[15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4999) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6078) -> -[15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 256) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 3920) -> -[10000 ps] ACT @ (4, 2840) -> [ 5000 ps] RD @ (0, 256) -> [10000 ps] RD @ (4, 256) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1761) -> -[15000 ps] RD @ (4, 256) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15987) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 682) -> -[15000 ps] RD @ (4, 256) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14908) -> -[10000 ps] ACT @ (4, 13828) -> [ 5000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 11670) -> [10000 ps] ACT @ (4, 12749) -> [15000 ps] RD @ (4, 248) -> [10000 ps] RD @ (0, 248) -> [17500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10591) -> [15000 ps] RD @ (0, 248) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8432) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9512) -> [15000 ps] RD @ (0, 248) -> [10000 ps] RD @ (4, 248) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7353) -> [10000 ps] ACT @ (0, 6274) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5195) -> [15000 ps] RD @ (0, 240) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3036) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4116) -> [15000 ps] RD @ (0, 240) -> [10000 ps] RD @ (4, 240) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 1957) -> [10000 ps] ACT @ (0, 878) -> [ 5000 ps] RD @ (4, 240) -> [10000 ps] RD @ (0, 240) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16183) -> [15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14024) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15104) -> [15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 12945) -> [10000 ps] ACT @ (0, 11866) -> [ 5000 ps] RD @ (4, 232) -> [10000 ps] RD @ (0, 232) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10787) -> [15000 ps] RD @ (0, 232) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8628) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 9708) -> [15000 ps] RD @ (0, 232) -> [10000 ps] RD @ (4, 232) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 7549) -> [10000 ps] ACT @ (0, 6470) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5391) -> [15000 ps] RD @ (0, 224) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3232) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 4312) -> [15000 ps] RD @ (0, 224) -> [10000 ps] RD @ (4, 224) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 2153) -> [10000 ps] ACT @ (0, 1074) -> [ 5000 ps] RD @ (4, 224) -> [10000 ps] RD @ (0, 224) -> [27500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16379) -> [15000 ps] RD @ (0, 216) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14220) -> [ 2500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15300) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 13141) -> [10000 ps] ACT @ (0, 12062) -> [ 5000 ps] RD @ (4, 216) -> [10000 ps] RD @ (0, 216) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9903) -> [10000 ps] ACT @ (0, 10983) -> [15000 ps] RD @ (0, 216) -> [10000 ps] RD @ (4, 216) -> -[17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8824) -> [15000 ps] RD @ (4, 216) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6666) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7745) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5587) -> [10000 ps] ACT @ (4, 4507) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 208) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3428) -> [15000 ps] RD @ (4, 208) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1270) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2349) -> [15000 ps] RD @ (4, 208) -> [10000 ps] RD @ (0, 208) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 191) -> [10000 ps] ACT @ (4, 15495) -> [ 5000 ps] RD @ (0, 208) -> [10000 ps] RD @ (4, 200) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14416) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12258) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13337) -> [15000 ps] RD @ (4, 200) -> [10000 ps] RD @ (0, 200) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11179) -> [10000 ps] ACT @ (4, 10099) -> [ 5000 ps] RD @ (0, 200) -> [10000 ps] RD @ (4, 200) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9020) -> [15000 ps] RD @ (4, 200) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6862) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7941) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5783) -> [10000 ps] ACT @ (4, 4703) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 192) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3624) -> [15000 ps] RD @ (4, 192) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1466) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2545) -> [15000 ps] RD @ (4, 192) -> [10000 ps] RD @ (0, 192) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 387) -> [10000 ps] ACT @ (4, 15691) -> [ 5000 ps] RD @ (0, 192) -> [10000 ps] RD @ (4, 184) -> -[27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14612) -> [15000 ps] RD @ (4, 184) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12454) -> -[ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13533) -> [15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 184) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11375) -> [10000 ps] ACT @ (4, 10295) -> [ 5000 ps] RD @ (0, 184) -> [ 7500 ps] NOP -> -[ 2500 ps] RD @ (4, 184) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 8137) -> [10000 ps] ACT @ (4, 9216) -> -[15000 ps] RD @ (4, 184) -> [10000 ps] RD @ (0, 176) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (0, 7058) -> [15000 ps] RD @ (0, 176) -> [ 5000 ps] ACT @ (4, 4899) -> [22500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5979) -> -[15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 176) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 3820) -> -[10000 ps] ACT @ (0, 2741) -> [ 5000 ps] RD @ (4, 176) -> [10000 ps] RD @ (0, 176) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1662) -> -[15000 ps] RD @ (0, 176) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 15887) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 583) -> -[15000 ps] RD @ (0, 176) -> [10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 14808) -> -[10000 ps] ACT @ (0, 13729) -> [ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12650) -> -[15000 ps] RD @ (0, 168) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10491) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11571) -> -[15000 ps] RD @ (0, 168) -> [10000 ps] RD @ (4, 168) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9412) -> -[10000 ps] ACT @ (0, 8333) -> [ 5000 ps] RD @ (4, 168) -> [10000 ps] RD @ (0, 168) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7254) -> -[15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 5095) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 6175) -> -[15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 160) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 4016) -> -[10000 ps] ACT @ (0, 2937) -> [ 5000 ps] RD @ (4, 160) -> [10000 ps] RD @ (0, 160) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1858) -> -[15000 ps] RD @ (0, 160) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 16083) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 779) -> -[15000 ps] RD @ (0, 160) -> [10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15004) -> -[10000 ps] ACT @ (0, 13925) -> [ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12846) -> -[15000 ps] RD @ (0, 152) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 10687) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11767) -> -[15000 ps] RD @ (0, 152) -> [10000 ps] RD @ (4, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 9608) -> -[10000 ps] ACT @ (0, 8529) -> [ 5000 ps] RD @ (4, 152) -> [10000 ps] RD @ (0, 152) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> -[ 7500 ps] ACT @ (4, 6370) -> [10000 ps] ACT @ (0, 7450) -> [15000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [17500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5291) -> [15000 ps] RD @ (4, 144) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3133) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4212) -> [15000 ps] RD @ (4, 144) -> [10000 ps] RD @ (0, 144) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2054) -> [10000 ps] ACT @ (4, 974) -> [ 5000 ps] RD @ (0, 144) -> [10000 ps] RD @ (4, 144) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 16279) -> [15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14121) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15200) -> [15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13042) -> [10000 ps] ACT @ (4, 11962) -> [ 5000 ps] RD @ (0, 136) -> [10000 ps] RD @ (4, 136) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10883) -> [15000 ps] RD @ (4, 136) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8725) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 9804) -> [15000 ps] RD @ (4, 136) -> [10000 ps] RD @ (0, 136) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7646) -> [10000 ps] ACT @ (4, 6566) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 5487) -> [15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3329) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 4408) -> [15000 ps] RD @ (4, 128) -> [10000 ps] RD @ (0, 128) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 2250) -> [10000 ps] ACT @ (4, 1170) -> [ 5000 ps] RD @ (0, 128) -> [10000 ps] RD @ (4, 128) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 91) -> [15000 ps] RD @ (4, 128) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14317) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 15396) -> [15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 13238) -> [10000 ps] ACT @ (4, 12158) -> [ 5000 ps] RD @ (0, 120) -> [10000 ps] RD @ (4, 120) -> [27500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 11079) -> [15000 ps] RD @ (4, 120) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8921) -> [ 2500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 10000) -> [15000 ps] RD @ (4, 120) -> [10000 ps] RD @ (0, 120) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> -[ 7500 ps] ACT @ (0, 7842) -> [10000 ps] ACT @ (4, 6762) -> [ 5000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (0) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4604) -> [10000 ps] ACT @ (4, 5683) -> [15000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 112) -> -[17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3525) -> [15000 ps] RD @ (0, 112) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1366) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2446) -> [15000 ps] RD @ (0, 112) -> [10000 ps] RD @ (4, 112) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 287) -> [10000 ps] ACT @ (0, 15592) -> [ 5000 ps] RD @ (4, 112) -> [10000 ps] RD @ (0, 104) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14513) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12354) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13434) -> [15000 ps] RD @ (0, 104) -> [10000 ps] RD @ (4, 104) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11275) -> [10000 ps] ACT @ (0, 10196) -> [ 5000 ps] RD @ (4, 104) -> [10000 ps] RD @ (0, 104) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9117) -> [15000 ps] RD @ (0, 104) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6958) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8038) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 5879) -> [10000 ps] ACT @ (0, 4800) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 96) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 3721) -> [15000 ps] RD @ (0, 96) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1562) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 2642) -> [15000 ps] RD @ (0, 96) -> [10000 ps] RD @ (4, 96) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 483) -> [10000 ps] ACT @ (0, 15788) -> [ 5000 ps] RD @ (4, 96) -> [10000 ps] RD @ (0, 88) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 14709) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12550) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13630) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 88) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 11471) -> [10000 ps] ACT @ (0, 10392) -> [ 5000 ps] RD @ (4, 88) -> [10000 ps] RD @ (0, 88) -> -[27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9313) -> [15000 ps] RD @ (0, 88) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7154) -> -[ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 8234) -> [15000 ps] RD @ (0, 88) -> [10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 6075) -> [10000 ps] ACT @ (0, 4996) -> [ 5000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 80) -> -[17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2837) -> [10000 ps] ACT @ (0, 3917) -> [15000 ps] RD @ (0, 80) -> -[10000 ps] RD @ (4, 80) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1758) -> [15000 ps] RD @ (4, 80) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 15984) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 679) -> [15000 ps] RD @ (4, 80) -> [10000 ps] RD @ (0, 72) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 14905) -> [10000 ps] ACT @ (4, 13825) -> [ 5000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12746) -> [15000 ps] RD @ (4, 72) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10588) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11667) -> [15000 ps] RD @ (4, 72) -> [10000 ps] RD @ (0, 72) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9509) -> [10000 ps] ACT @ (4, 8429) -> [ 5000 ps] RD @ (0, 72) -> -[10000 ps] RD @ (4, 72) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7350) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5192) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6271) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 64) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4113) -> [10000 ps] ACT @ (4, 3033) -> [ 5000 ps] RD @ (0, 64) -> -[10000 ps] RD @ (4, 64) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 1954) -> [15000 ps] RD @ (4, 64) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16180) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 875) -> [15000 ps] RD @ (4, 64) -> [10000 ps] RD @ (0, 56) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 15101) -> [10000 ps] ACT @ (4, 14021) -> [ 5000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12942) -> [15000 ps] RD @ (4, 56) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10784) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 11863) -> [15000 ps] RD @ (4, 56) -> [10000 ps] RD @ (0, 56) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 9705) -> [10000 ps] ACT @ (4, 8625) -> [ 5000 ps] RD @ (0, 56) -> -[10000 ps] RD @ (4, 56) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 7546) -> [15000 ps] RD @ (4, 48) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5388) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 6467) -> [15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> -[17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 4309) -> [10000 ps] ACT @ (4, 3229) -> [ 5000 ps] RD @ (0, 48) -> -[10000 ps] RD @ (4, 48) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 1071) -> [10000 ps] ACT @ (4, 2150) -> -[15000 ps] RD @ (4, 48) -> [10000 ps] RD @ (0, 48) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 16376) -> [15000 ps] RD @ (0, 40) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14217) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15297) -> [15000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13138) -> [10000 ps] ACT @ (0, 12059) -> -[ 5000 ps] RD @ (4, 40) -> [10000 ps] RD @ (0, 40) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10980) -> [15000 ps] RD @ (0, 40) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8821) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 9901) -> [15000 ps] RD @ (0, 40) -> -[10000 ps] RD @ (4, 40) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7742) -> [10000 ps] ACT @ (0, 6663) -> -[ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5584) -> [15000 ps] RD @ (0, 32) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3425) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4505) -> [15000 ps] RD @ (0, 32) -> -[10000 ps] RD @ (4, 32) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2346) -> [10000 ps] ACT @ (0, 1267) -> -[ 5000 ps] RD @ (4, 32) -> [10000 ps] RD @ (0, 32) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 188) -> [15000 ps] RD @ (0, 32) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14413) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 15493) -> [15000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 13334) -> [10000 ps] ACT @ (0, 12255) -> -[ 5000 ps] RD @ (4, 24) -> [10000 ps] RD @ (0, 24) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 11176) -> [15000 ps] RD @ (0, 24) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9017) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10097) -> [15000 ps] RD @ (0, 24) -> -[10000 ps] RD @ (4, 24) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 7938) -> [10000 ps] ACT @ (0, 6859) -> -[ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> [27500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 5780) -> [15000 ps] RD @ (0, 16) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3621) -> [ 2500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 4701) -> [15000 ps] RD @ (0, 16) -> -[10000 ps] RD @ (4, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 2542) -> [10000 ps] ACT @ (0, 1463) -> -[ 5000 ps] RD @ (4, 16) -> [10000 ps] RD @ (0, 16) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (4, 15688) -> -[10000 ps] ACT @ (0, 384) -> [15000 ps] RD @ (0, 16) -> [10000 ps] RD @ (4, 8) -> [17500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14609) -> -[15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 12451) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 13530) -> -[15000 ps] RD @ (4, 8) -> [10000 ps] RD @ (0, 8) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 11372) -> -[10000 ps] ACT @ (4, 10292) -> [ 5000 ps] RD @ (0, 8) -> [10000 ps] RD @ (4, 8) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 9213) -> -[15000 ps] RD @ (4, 8) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 7055) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 8134) -> -[15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (0, 5976) -> -[10000 ps] ACT @ (4, 4896) -> [ 5000 ps] RD @ (0, 0) -> [10000 ps] RD @ (4, 0) -> [27500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 3817) -> -[15000 ps] RD @ (4, 0) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 1659) -> [ 2500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 2738) -> -[15000 ps] RD @ (4, 0) -> [10000 ps] RD @ (0, 0) -> [17500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 580) -> [15000 ps] RD @ (0, 0) -> -[ 5000 ps] ACT @ (7, 15884) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 13727) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14805) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 12647) -> [ 2500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 13726) -> [15000 ps] RD @ (7, 1016) -> [ 5000 ps] ACT @ (3, 12647) -> [ 2500 ps] PRE @ (4) -> [12500 ps] RD @ (3, 1016) -> -[ 7500 ps] PRE @ (0) -> [17500 ps] ACT @ (0, 10489) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11568) -> [15000 ps] RD @ (3, 1016) -> -[ 7500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10488) -> [10000 ps] ACT @ (0, 9410) -> [ 5000 ps] RD @ (7, 1016) -> -[27500 ps] PRE @ (7) -> [10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 9409) -> [10000 ps] ACT @ (0, 8331) -> [ 5000 ps] RD @ (7, 1016) -> -[ 5000 ps] ACT @ (4, 7251) -> [22500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8330) -> [15000 ps] RD @ (7, 1016) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7251) -> [10000 ps] ACT @ (4, 6172) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5093) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6172) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5092) -> [10000 ps] ACT @ (0, 4014) -> [ 5000 ps] RD @ (7, 1008) -> [27500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 4013) -> [10000 ps] ACT @ (0, 2935) -> [ 5000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 1855) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2934) -> [15000 ps] RD @ (7, 1008) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 1855) -> [10000 ps] ACT @ (4, 776) -> [ 5000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 16081) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 776) -> [15000 ps] RD @ (3, 1008) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 16080) -> [10000 ps] ACT @ (0, 15002) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 13922) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15001) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13922) -> [10000 ps] ACT @ (4, 12843) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 12843) -> [10000 ps] ACT @ (4, 11764) -> [ 5000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 10685) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11764) -> [15000 ps] RD @ (3, 1000) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10684) -> [10000 ps] ACT @ (0, 9606) -> [ 5000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8526) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9605) -> [15000 ps] RD @ (7, 1000) -> [ 7500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 8526) -> [10000 ps] ACT @ (4, 7447) -> [ 5000 ps] RD @ (3, 1000) -> [27500 ps] PRE @ (3) -> -[10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 7447) -> [10000 ps] ACT @ (4, 6368) -> [ 5000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (0) -> -[17500 ps] ACT @ (0, 5289) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6368) -> [15000 ps] RD @ (3, 992) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 5288) -> [10000 ps] ACT @ (0, 4210) -> [ 5000 ps] RD @ (7, 992) -> [27500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 4209) -> [15000 ps] RD @ (7, 992) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (4, 3130) -> [10000 ps] ACT @ (3, 3130) -> [15000 ps] RD @ (3, 992) -> [17500 ps] PRE @ (4) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (4, 972) -> [10000 ps] ACT @ (3, 2051) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (0, 16277) -> [22500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 972) -> [15000 ps] RD @ (3, 992) -> [ 5000 ps] ACT @ (7, 16276) -> [ 2500 ps] PRE @ (0) -> [12500 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (4) -> [17500 ps] ACT @ (4, 14118) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15197) -> [15000 ps] RD @ (7, 984) -> -[ 7500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 14118) -> [10000 ps] ACT @ (4, 13039) -> [ 5000 ps] RD @ (3, 984) -> -[27500 ps] PRE @ (3) -> [10000 ps] PRE @ (4) -> [ 7500 ps] ACT @ (3, 13039) -> [10000 ps] ACT @ (4, 11960) -> [ 5000 ps] RD @ (3, 984) -> -[ 5000 ps] ACT @ (0, 10881) -> [22500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11960) -> [15000 ps] RD @ (3, 984) -> [ 7500 ps] PRE @ (7) -> -[10000 ps] PRE @ (0) -> [ 7500 ps] ACT @ (7, 10880) -> [10000 ps] ACT @ (0, 9802) -> [ 5000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (4) -> -[17500 ps] ACT @ (4, 8722) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9801) -> [15000 ps] RD @ (7, 984) -> [ 7500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8722) -> [15000 ps] RD @ (3, 984) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7643) -> [15000 ps] RD @ (3, 976) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5484) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6564) -> [15000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4405) -> [10000 ps] ACT @ (3, 3326) -> -[ 5000 ps] RD @ (7, 976) -> [10000 ps] RD @ (3, 976) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2247) -> [15000 ps] RD @ (3, 976) -> -[ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 88) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1168) -> [15000 ps] RD @ (3, 976) -> -[10000 ps] RD @ (7, 976) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15393) -> [10000 ps] ACT @ (3, 14314) -> -[ 5000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 12155) -> -[10000 ps] ACT @ (3, 13235) -> [15000 ps] RD @ (3, 968) -> [10000 ps] RD @ (7, 968) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11076) -> -[15000 ps] RD @ (7, 968) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 8918) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9997) -> -[15000 ps] RD @ (7, 968) -> [10000 ps] RD @ (3, 968) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 7839) -> -[10000 ps] ACT @ (7, 6759) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5680) -> -[15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3522) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4601) -> -[15000 ps] RD @ (7, 960) -> [10000 ps] RD @ (3, 960) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2443) -> -[10000 ps] ACT @ (7, 1363) -> [ 5000 ps] RD @ (3, 960) -> [10000 ps] RD @ (7, 960) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 284) -> -[15000 ps] RD @ (7, 960) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14510) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15589) -> -[15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13431) -> -[10000 ps] ACT @ (7, 12351) -> [ 5000 ps] RD @ (3, 952) -> [10000 ps] RD @ (7, 952) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11272) -> -[15000 ps] RD @ (7, 952) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 9114) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 10193) -> -[15000 ps] RD @ (7, 952) -> [10000 ps] RD @ (3, 952) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 8035) -> -[10000 ps] ACT @ (7, 6955) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5876) -> -[15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 3718) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4797) -> -[15000 ps] RD @ (7, 944) -> [10000 ps] RD @ (3, 944) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 2639) -> -[10000 ps] ACT @ (7, 1559) -> [ 5000 ps] RD @ (3, 944) -> [10000 ps] RD @ (7, 944) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 480) -> -[15000 ps] RD @ (7, 944) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 14706) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15785) -> -[15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 13627) -> -[10000 ps] ACT @ (7, 12547) -> [ 5000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 936) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> -[ 7500 ps] ACT @ (3, 10389) -> [10000 ps] ACT @ (7, 11468) -> [15000 ps] RD @ (7, 936) -> [10000 ps] RD @ (3, 936) -> [17500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9310) -> [15000 ps] RD @ (3, 936) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7151) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8231) -> [15000 ps] RD @ (3, 936) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 6072) -> [10000 ps] ACT @ (3, 4993) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 928) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3914) -> [15000 ps] RD @ (3, 928) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1755) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 2835) -> [15000 ps] RD @ (3, 928) -> [10000 ps] RD @ (7, 928) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 676) -> [10000 ps] ACT @ (3, 15981) -> [ 5000 ps] RD @ (7, 928) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14902) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12743) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 13823) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 920) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 11664) -> [10000 ps] ACT @ (3, 10585) -> [ 5000 ps] RD @ (7, 920) -> [10000 ps] RD @ (3, 920) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 9506) -> [15000 ps] RD @ (3, 920) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7347) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 8427) -> [15000 ps] RD @ (3, 920) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 6268) -> [10000 ps] ACT @ (3, 5189) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 912) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 4110) -> [15000 ps] RD @ (3, 912) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1951) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 3031) -> [15000 ps] RD @ (3, 912) -> [10000 ps] RD @ (7, 912) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 872) -> [10000 ps] ACT @ (3, 16177) -> [ 5000 ps] RD @ (7, 912) -> [10000 ps] RD @ (3, 904) -> [27500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 15098) -> [15000 ps] RD @ (3, 904) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12939) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 14019) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> -[ 7500 ps] ACT @ (7, 11860) -> [10000 ps] ACT @ (3, 10781) -> [ 5000 ps] RD @ (7, 904) -> [10000 ps] RD @ (3, 904) -> [17500 ps] PRE @ (7) -> -[10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8622) -> [10000 ps] ACT @ (3, 9702) -> [15000 ps] RD @ (3, 904) -> [10000 ps] RD @ (7, 904) -> -[17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7543) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5385) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6464) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 896) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4306) -> [10000 ps] ACT @ (7, 3226) -> [ 5000 ps] RD @ (3, 896) -> [10000 ps] RD @ (7, 896) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2147) -> [15000 ps] RD @ (7, 896) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 16373) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1068) -> [15000 ps] RD @ (7, 896) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15294) -> [10000 ps] ACT @ (7, 14214) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13135) -> [15000 ps] RD @ (7, 888) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10977) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12056) -> [15000 ps] RD @ (7, 888) -> [10000 ps] RD @ (3, 888) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 9898) -> [10000 ps] ACT @ (7, 8818) -> [ 5000 ps] RD @ (3, 888) -> [10000 ps] RD @ (7, 888) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 7739) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5581) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 6660) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 4502) -> [10000 ps] ACT @ (7, 3422) -> [ 5000 ps] RD @ (3, 880) -> [10000 ps] RD @ (7, 880) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2343) -> [15000 ps] RD @ (7, 880) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 185) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 1264) -> [15000 ps] RD @ (7, 880) -> [10000 ps] RD @ (3, 880) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 15490) -> [10000 ps] ACT @ (7, 14410) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> -[27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13331) -> [15000 ps] RD @ (7, 872) -> [ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11173) -> -[ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 12252) -> [15000 ps] RD @ (7, 872) -> [10000 ps] RD @ (3, 872) -> [17500 ps] PRE @ (3) -> -[10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 10094) -> [10000 ps] ACT @ (7, 9014) -> [ 5000 ps] RD @ (3, 872) -> [10000 ps] RD @ (7, 872) -> -[17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6856) -> [10000 ps] ACT @ (7, 7935) -> [15000 ps] RD @ (7, 864) -> -[10000 ps] RD @ (3, 864) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5777) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3618) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4698) -> [15000 ps] RD @ (3, 864) -> [10000 ps] RD @ (7, 864) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2539) -> [10000 ps] ACT @ (3, 1460) -> [ 5000 ps] RD @ (7, 864) -> -[10000 ps] RD @ (3, 864) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 381) -> [15000 ps] RD @ (3, 864) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14606) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15686) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13527) -> [10000 ps] ACT @ (3, 12448) -> [ 5000 ps] RD @ (7, 856) -> -[10000 ps] RD @ (3, 856) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11369) -> [15000 ps] RD @ (3, 856) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9210) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10290) -> [15000 ps] RD @ (3, 856) -> [10000 ps] RD @ (7, 856) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8131) -> [10000 ps] ACT @ (3, 7052) -> [ 5000 ps] RD @ (7, 848) -> -[10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 5973) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 3814) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 4894) -> [15000 ps] RD @ (3, 848) -> [10000 ps] RD @ (7, 848) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 2735) -> [10000 ps] ACT @ (3, 1656) -> [ 5000 ps] RD @ (7, 848) -> -[10000 ps] RD @ (3, 848) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 577) -> [15000 ps] RD @ (3, 848) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 14802) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 15882) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 13723) -> [10000 ps] ACT @ (3, 12644) -> [ 5000 ps] RD @ (7, 840) -> -[10000 ps] RD @ (3, 840) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 11565) -> [15000 ps] RD @ (3, 840) -> [ 7500 ps] PRE @ (7) -> -[17500 ps] ACT @ (7, 9406) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 10486) -> [15000 ps] RD @ (3, 840) -> [10000 ps] RD @ (7, 840) -> -[17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 8327) -> [10000 ps] ACT @ (3, 7248) -> [ 5000 ps] RD @ (7, 840) -> -[10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 5089) -> [10000 ps] ACT @ (3, 6169) -> -[15000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 832) -> [17500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4010) -> [15000 ps] RD @ (7, 832) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1852) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 2931) -> [15000 ps] RD @ (7, 832) -> -[10000 ps] RD @ (3, 832) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 773) -> [10000 ps] ACT @ (7, 16077) -> -[ 5000 ps] RD @ (3, 832) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14998) -> [15000 ps] RD @ (7, 824) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12840) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 13919) -> [15000 ps] RD @ (7, 824) -> -[10000 ps] RD @ (3, 824) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11761) -> [10000 ps] ACT @ (7, 10681) -> -[ 5000 ps] RD @ (3, 824) -> [10000 ps] RD @ (7, 824) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9602) -> [15000 ps] RD @ (7, 824) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7444) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8523) -> [15000 ps] RD @ (7, 824) -> -[10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6365) -> [10000 ps] ACT @ (7, 5285) -> -[ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 816) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 4206) -> [15000 ps] RD @ (7, 816) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2048) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 3127) -> [15000 ps] RD @ (7, 816) -> -[10000 ps] RD @ (3, 816) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 969) -> [10000 ps] ACT @ (7, 16273) -> -[ 5000 ps] RD @ (3, 816) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 15194) -> [15000 ps] RD @ (7, 808) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13036) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 14115) -> [15000 ps] RD @ (7, 808) -> -[10000 ps] RD @ (3, 808) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 11957) -> [10000 ps] ACT @ (7, 10877) -> -[ 5000 ps] RD @ (3, 808) -> [10000 ps] RD @ (7, 808) -> [27500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 9798) -> [15000 ps] RD @ (7, 808) -> -[ 7500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7640) -> [ 2500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 8719) -> [15000 ps] RD @ (7, 808) -> -[10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 6561) -> [10000 ps] ACT @ (7, 5481) -> -[ 5000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (3) -> [10000 ps] PRE @ (7) -> [ 7500 ps] ACT @ (3, 3323) -> -[10000 ps] ACT @ (7, 4402) -> [15000 ps] RD @ (7, 800) -> [10000 ps] RD @ (3, 800) -> [17500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2244) -> -[15000 ps] RD @ (3, 800) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 85) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1165) -> -[15000 ps] RD @ (3, 800) -> [10000 ps] RD @ (7, 800) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15390) -> -[10000 ps] ACT @ (3, 14311) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13232) -> -[15000 ps] RD @ (3, 792) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11073) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12153) -> -[15000 ps] RD @ (3, 792) -> [10000 ps] RD @ (7, 792) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 9994) -> -[10000 ps] ACT @ (3, 8915) -> [ 5000 ps] RD @ (7, 792) -> [10000 ps] RD @ (3, 792) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 7836) -> -[15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5677) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 6757) -> -[15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 4598) -> -[10000 ps] ACT @ (3, 3519) -> [ 5000 ps] RD @ (7, 784) -> [10000 ps] RD @ (3, 784) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 2440) -> -[15000 ps] RD @ (3, 784) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 281) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 1361) -> -[15000 ps] RD @ (3, 784) -> [10000 ps] RD @ (7, 784) -> [17500 ps] PRE @ (7) -> [10000 ps] PRE @ (3) -> [ 7500 ps] ACT @ (7, 15586) -> -[10000 ps] ACT @ (3, 14507) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 13428) -> -[15000 ps] RD @ (3, 776) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 11269) -> [ 2500 ps] PRE @ (3) -> [17500 ps] ACT @ (3, 12349) -> -[15000 ps] RD @ (3, 776) -> [10000 ps] RD @ (7, 776) -> [67500 ps] PRE @ (0) -> [30000 ps] REF -> [360000 ps] NOP -> -[17500 ps] ACT @ (7, 10190) -> [10000 ps] ACT @ (3, 9111) -> [ 5000 ps] RD @ (7, 776) -> [10000 ps] RD @ (3, 776) -> [27500 ps] PRE @ (3) -> - --------------------------------- -DONE TEST 2: RANDOM -Number of Operations: 2304 -Time Started: 124100 ns -Time Done: 233710 ns -Average Rate: 47 ns/request --------------------------------- - - -[17500 ps] ACT @ (3, 8032) -> [15000 ps] RD @ (3, 768) -> [ 7500 ps] PRE @ (7) -> [17500 ps] ACT @ (7, 5873) -> [ 2500 ps] PRE @ (3) -> -[17500 ps] ACT @ (3, 6953) -> [15000 ps] RD @ (3, 768) -> [10000 ps] RD @ (7, 768) -> FAILED: Address = 18962384, expected data = 8fa2201f8fa1121f8fa0041f8f9ef61f8f9dea1f8f9cdc1f8f9bce1f8f9ac01f8f99b21f8f98a41f8f97961f8f96881f8f957a1f8f946c1f8f93601f8f92521f, read data = 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000123456789 @ 233840000.0 ps - - -------- SUMMARY ------- -Number of Writes = 4608 -Number of Reads = 4608 -Number of Success = 4604 -Number of Fails = 4 -Number of Injected Errors = 4 - -$stop called at time : 234810 ns : File "/home/angelo/Desktop/switch_fpga/DDR3_Controller/testbench/ddr3_dimm_micron_sim.v" Line 456 -run: Time (s): cpu = 00:00:15 ; elapsed = 00:44:56 . Memory (MB): peak = 2833.148 ; gain = 8.004 ; free physical = 1358 ; free virtual = 24780 -## quit -INFO: xsimkernel Simulation Memory Usage: 305696 KB (Peak: 371232 KB), Simulation CPU Usage: 2640970 ms -INFO: [Common 17-206] Exiting xsim at Wed Jul 5 15:46:48 2023...